Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2786

Precision Clock Frame Sync Synchronization 2 Register
The register allows programs to synchronize the clock frame sync units with external frame syncs.
PCG_SYNC2
Note that the PCG_CTLD1.CLKSRC bit is overridden if PCG_SYNC2.CLKDSRC bit in the
ter is set.
FSCSRC (R/W)
Frame Sync Source
CLKCSRC (R/W)
Clock C Source
FSDSRC (R/W)
Frame Sync D Source
CLKDSRC (R/W)
Clock D Source
Figure 35-18: PCG_SYNC2 Register Diagram
Table 35-15: PCG_SYNC2 Register Fields
Bit No.
(Access)
19 FSDSRC
(R/W)
18 CLKDSRC
(R/W)
17 CLKD
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15 14 13 12 11 10
0 0 0 0 0 0
31 30 29 28 27 26
0 0 0 0 0 0
Bit Name
Frame Sync D Source.
The PCG_SYNC2.FSDSRC bit enables the frame sync D input source.
Clock D Source.
The PCG_SYNC2.CLKDSRC bit enables the clock D input source.
Clock D Enable.
The PCG_SYNC2.CLKD bit enables synchronization of clock D with the external
frame sync.
9 8 7 6 5 4 3 2
0 0 0 0 0 0 0 0
25 24 23 22 21 20 19 18
0 0 0 0 0 0 0 0
Description/Enumeration
0 Output selected by FSDSOURCE bit
1 Clock derived from core PLL selected for frame sync D
0 Output selected by CLKDSOURCE bit
1 Clock derived from core PLL selected for clock D
0 Clock disabled
1 Clock enabled
ADSP-SC58x PCG Register Descriptions
PCG_SYNC2
1 0
0 0
FSC (R/W)
Frame Sync C Enable
CLKC (R/W)
Clock C Enable
17 16
0 0
FSD (R/W)
Frame Sync D Enable
CLKD (R/W)
Clock D Enable
regis-
35–27