Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2783

ADSP-SC58x PCG Register Descriptions
Table 35-13: PCG_PW2 Register Fields (Continued)
Bit No.
(Access)
0 STROBEC
(R/W)
35–24
Bit Name
One Shot Frame Sync PCG C.
The PCG_PW2.STROBEC bit sets the frame sync pulse for PCG C in bypass mode.
This is the duration equal to one period of the DAI_MISCA3_I signal (PCG C) re-
peating at the beginning of every frame.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration