Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2805

ADSP-SC58x ASRC Register Descriptions
Table 36-5: ASRC_CTL23 Register Fields
Bit No.
(Access)
31 EN3
(R/W)
30 MPHASE3
(R/W)
29:28 LENOUT3
(R/W)
27:26 SMODEOUT3
(R/W)
25 DITHER3
(R/W)
36–18
Bit Name
Enable SRC 3.
The ASRC_CTL23.EN3 bit enables SRC 3. When (set =1), or when the sample rate
(frame sync) between the input and output changes, the SRC begins its initialization
routine where; 1) MUTE_OUT is asserted, 2) soft mute control counter for input
samples is set to maximum attenuation (144 dB).
Note that SRC power-up completion is finished by clearing the
ASRC_RAT23.MUTEOUT3 bit.
Writes to the
ASRC_CTL23.EN3 bit. When setting and clearing this bit, it should be held low for
a minimum of 5 CLK cycles.
Matched-phase Mode 3.
The ASRC_CTL23.MPHASE3 bit configures SRC3 to not use its own internally-
generated sample rate ratio but use an externally-generated ratio. Used with TDM da-
ta.
Length Output 3.
The ASRC_CTL23.LENOUT3 bit field selects the serial output word length on
SRC3.
Serial Mode Output 3.
The ASRC_CTL23.SMODEOUT3 bit field selects the serial output format on SRC3.
Dither Enable 3.
The ASRC_CTL23.DITHER3 bit enables dithering before truncation on SRC3
when a word length less than 24 bits is selected.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
register should be at least one cycle before setting the
ASRC_CTL23
0 Matched phase slave disabled
1 Matched phase slave enabled
0 24 bits
1 20 bits
2 18 bits
3 16 bits
0 Left-justified
1 I2S
2 TDM
3 Right-justified
0 Truncation only
1 Dithering before truncation