Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2823

Compressed or Non-linear Audio Data
words of zeros followed by a word consisting of 0xF872 and another word consisting of 0x4E1F. When this sync
code is detected, the SPDIF_RX_STAT.COMPMODE bits hold the information regarding type of compression.
The last two words of the sync code, 0xF872 and 0x4E1F, are called the preamble-A and preamble-B of the burst
preamble. Preamble-C of the burst preamble contains burst information and is captured and stored by the receiver.
Preamble-D of the burst preamble contains the length code and is captured by the receiver. Even if the validity bit or
bit 1 of byte 0 has been set, the receiver still looks for the sync code in order to record the preamble-C and D values.
Once the sync code has not been detected in 4096 frames, the preamble-C and D registers are set to zero.
Emphasized Audio Data
Determination as to whether the received audio data is emphasized or not is done in software using the channel
status bits as detailed below.
• In professional mode, (bit 0 of byte 0 = 1), channel status bits 2-4 of byte 0 indicate the audio data is empha-
sized if they are equal to 110 or 111.
• In consumer mode, (bit 0 of byte 0 = 0), channel status bits 3-5 indicate the audio data is emphasized if they
are equal to 100, 010 or 110.
Single-Channel Double-Frequency Mode
Unlike previous processors, support for single-channel, double-frequency mode (SCDF) is not supported through
specific bits within the SPDIF_RX_CTL
tion provided by the CS (channel status) bits.
• 0111 = single channel double frequency mode
• 1000 = single channel double frequency mode-stereo left
• 1001 = single channel double frequency mode-stereo right
Clock Recovery Modes
The S/PDIF receiver extracts audio data, channel status, and user bits from the biphase encoded AES3 and S/PDIF
stream. In addition, a 50% duty cycle reference clock running at the sampling rate of the audio input data is gener-
ated for the receiver to recover the oversampling clock.
Number Controlled Oscillator
The receiver can recover the clock from the biphase encoded stream using an on-chip NCO shown in the following
figure. Note the dedicated NCO is separate from the PLL that supplies the clock to the processor core and which is
the default operation of the receiver.
37–10
register, but rather have to be implemented in software using the informa-
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference