Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2894

Data Transfer Modes
Two-Dimensional DMA
Register-based flow modes and descriptor-based flow modes support two-dimensional data transfers.
In two-dimensional (2D) mode, the X-direction count (DMA_XCNT), the X-direction modifier (DMA_XMOD), the
Y-direction count (DMA_YCNT), and the Y-direction modifier (DMA_YMOD) support arbitrary row and column
sizes. Also, the modify values can be negative, allowing implementation of interleaved data streams. The
DMA_XCNT value specifies the row size, and the
value must be 2 or greater.
The DMA start address (DMA_ADDRSTART), the X-direction modifier (DMA_XMOD), and theY-direction modifier
(DMA_YMOD) specifications all are in bytes. The alignment must be a multiple of the DMA transfer word size; con-
figured using the DMA_CFG.MSIZE bit. Misalignment results in a DMA channel error.
The DMA_XMOD register value is the byte-address increment that the channel applies after each transfer, decrement-
ing the register. The channel does not apply the
DMA_XCNT
DMA_XCNT_CUR register decrementing to 0 from 1. Except, the channel does apply the
transfer, when the
DMA_YCNT
The register value is the byte-address increment that the channel applies after each decrement of the
DMA_YMOD
value in DMA_YCNT_CUR. However, the channel does not apply the
on which the outer loop count (DMA_YCNT_CUR) also expires by decrementing from 1 to 0.
After the last transfer completes,
current address points to the last items address plus the
ming selects automatic refresh (such as in autobuffer mode), the channel reloads the DMA_XCNT_CUR,
DMA_YCNT_CUR, and
Interrupt notification is configurable for end-of-row or end-of-work unit completion.
For example, two-dimensional DMA can be used to extract interleaved data (such as RGB values for a video frame )
by modifying both of the
ample depicts the process of receiving a stream of the R, G, B values from an N*M frame. The inner loop of the 2D
DMA configuration has three values
sive elements in each row are 1-2-3, 4-5-6 and so forth. The outer loop of the 2D DMA configuration has N*M
values (DMA_YCNT = N*M) and a negative stride ( DMA_YMOD) of 1-2*N*M chosen to instruct the DMA control-
ler to jump from element 3 to 4, 6 to 7 and so forth at the end of each inner loop.
3 6
2 5
1 4
M
N
Figure 38-4: Capturing a Video Data Stream 2D DMA Example
38–30
register is 1 and the
DMA_YCNT_CUR
for the first data transfer of the next work unit.
DMA_ADDR_CUR
and
DMA_XMOD DMA_YMOD
(DMA_XCNT
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DMA_YCNT value specifies the column size; where the
DMA_XCNT
register decrements from 1 to 0.
DMA_XCNT
DMA_YMOD
is 1 and the
DMA_XCNT_CUR
DMA_XMOD register value. If the DMA channel program-
values. The Capturing a Video Data Stream 2D DMA Ex-
= 3) and a stride (DMA_XMOD) of N*M, chosen such that succes-
when the inner loop count ends with the
DMA_XCNT
value to the last item in the array
register is 0. The DMA channels
DMA_XCNT
on the final