Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2912

ADSP-SC58x DMA Register Descriptions
Bandwidth Limit Count Current Register
The
DMA_BWLCNT_CUR
issued.
Figure 38-8: DMA_BWLCNT_CUR Register Diagram
Table 38-18: DMA_BWLCNT_CUR Register Fields
Bit No.
(Access)
15:0 VALUE
(R/NW)
38–48
register contains the number of SCLK count cycles remaining before the next request is
15 14 13 12
0 0 0
VALUE (R)
Bandwidth Limit Count Current
31 30 29 28
0 0 0
Bit Name
Bandwidth Limit Count Current.
The DMA_BWLCNT_CUR.VALUE bit field contains the number of SCLK count cy-
cles remaining before the next request is issued.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
11 10 9 8 7 6 5
0 0 0 0 0 0 0 0
27 26 25 24 23 22 21 20
0 0 0 0 0 0 0 0
Description/Enumeration
4 3 2 1 0
0 0 0 0 0
19 18 17 16
0 0 0 0 0