Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2883

• Clears the DMA_STAT.RUN bit field to stop DMA operation (if the flow was set to stop mode) and transfers
any remaining data in the FIFO of the DMA channel to the peripheral.
• Loads a new descriptor from memory into the DMA registers by way of the contents of the
DMA_DSCPTR_CUR
The channel takes the descriptor size from the DMA_CFG.NDSIZE value before the fetch.
• Copies the
DMA_DSCPTR_NXT
fetches the descriptor from the new contents of the
into the DMA registers while incrementing the
• Checks for detection of an incoming trigger event (for descriptor-on-demand array mode):
• If the channel detects a trigger event, the DMA channel loads a new descriptor from memory into the
DMA registers from the contents of the
DMA_DSCPTR_CUR
before the fetch.
• If the channel detects no trigger event, the DMA channel begins the next work unit by reloading the cur-
rent registers.
• Checks for detection of an incoming trigger event (for descriptor-on-demand list mode):
• If the channel detects a trigger event, the DMA channel copies the
the DMA_DSCPTR_CUR
and places the contents into the DMA registers while incrementing the
• If the channel detects no trigger event, the DMA channel begins the next work unit by reloading the cur-
rent registers as described in the next step.
• Begins the next work unit (if flow configuration is anything other than stop mode) by reloading the current
registers (DMA_ADDR_CUR, DMA_XCNT_CUR, and DMA_YCNT_CUR) from their descriptor registers
(DMA_ADDRSTART, DMA_XCNT, and DMA_YCNT)
Work Unit Transition Flow
The DMA_CFG.SYNC bit controls transitions from one work unit to the next work unit. In general, continuous
transitions have lower latency at the cost of restrictions on changes of data format or addressed memory space in the
two work units. These latency gains and data restrictions arise from the way the channel handles the DMA FIFO
while fetching the next descriptor.
In continuous transitions, with disabled synchronization, the DMA FIFO pipeline continues to transfer data to and
from the peripheral or destination memory. These transfers continue during the descriptor fetch and during the
DMA channel pause between descriptor chains. By comparison, synchronized transitions provide better real-time
synchronization of interrupts and triggers with a given peripheral state. Synchronized transitions also provide greater
flexibility in the data formats and memory spaces of the two work units. This flexibility comes at the cost of higher
latency in the transition. In synchronized transitions, the DMA FIFO pipeline drains to the destination or flushes
(received data discarded) between work units.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register (for descriptor-array mode) and increments the
register into the
DMA_DSCPTR_CUR
register. The channel takes the descriptor size from the DMA_CFG.NDSIZE value
register, fetches the descriptor memory from the
DMA_DSCPTR_CUR
DMA_DSCPTR_CUR
register.
DMA_DSCPTR_CUR
register, while incrementing the
DMA Channel Operation Flow
DMA_DSCPTR_CUR
register (for descriptor-list mode),
register, and places these contents
register value to
DMA_DSCPTR_NXT
DMA_DSCPTR_CUR
DMA_DSCPTR_CUR
register
register,
register.
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