Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2891

• The DMA controller autonomously loads the descriptor set from memory to the affected DMA controller reg-
isters on demand.
• The channel can fetch descriptor sets from any memory space that supports DMA read operations.
• The descriptor set describes the next operation that the DMA controller performs.
• The descriptor set can include information such as the DMA configuration word as well as data source or desti-
nation address, transfer count, and address modify values.
A descriptor set describes a single work unit. The next work unit can reuse some values from the previous one de-
scriptor set. But, this reusage is possible only if they are not overwritten in the subsequent descriptor set fetches and
only if the work unit requires the use of this descriptor.
The DMA channel supports the following flow modes with descriptor-based operations.
•
Descriptor-Array Mode
•
Descriptor-List Mode
•
Descriptor-On-Demand Modes
The DMA channel supports variable descriptor set sizes within the configuration. The size of a descriptor set can
contain as little as a single descriptor and the supported descriptor set sizes can differ between the various descriptor-
based flow modes. In addition to configurable descriptor set size, descriptor-based DMA also allows for altering of
the flow mode of the next descriptor set. Programs can transition from one descriptor-based mode to another de-
scriptor-based mode and can also transition to any of the register-based flow modes.
Descriptor-Array Mode
When configured in this mode, the descriptor sets do not contain further descriptor pointers. Software writes the
initial descriptor-pointer value, which points to an array of descriptors. This operation assumes that the individual
descriptors reside next to each other and assumes that their addresses are known.
The Offsets for Descriptor-Array Mode Parameters and Descriptors table illustrates how to structure a descriptor set
in memory. The descriptor sets must reside in a contiguous block or memory in the format shown in the table.
Locate the first descriptor of the next descriptor set in the memory location immediately following the last descrip-
tor of the current descriptor set. The values have the same order as the corresponding offset addresses of the memo-
ry-mapped register.
Table 38-9: Offsets for Descriptor -Array Mode Parameters and Descriptors
Descriptor Offset
0x00
0x04
0x08
0x0C
0x10
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Parameter Register
DMA_ADDRSTART
DMA_CFG
DMA_XCNT
DMA_XMOD
DMA_YCNT
Descriptor-Based Flow Modes
38–27