Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2802

Table 36-4: ASRC_CTL01 Register Fields (Continued)
Bit No.
(Access)
15 EN0
(R/W)
14 MPHASE0
(R/W)
13:12 LENOUT0
(R/W)
11:10 SMODEOUT0
(R/W)
9 DITHER0
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Enable SRC 0.
The ASRC_CTL01.EN0 bit enables SRC 0. When (set =1), or when the sample rate
(frame sync) between the input and output changes, the SRC begins its initialization
routine where; 1) MUTE_OUT is asserted, 2) soft mute control counter for input
samples is set to maximum attenuation (144 dB).
Note that SRC power-up completion is finished by clearing the
ASRC_RAT01.MUTEOUT0 bit.
Writes to the
ASRC_CTL01.EN0 bit. When setting and clearing this bit, it should be held low for
a minimum of 5 CLK cycles.
Matched-phase Mode 0.
The ASRC_CTL01.MPHASE0 bit configures SRC0 to not use its own internally-
generated sample rate ratio but use an externally-generated ratio. Used with TDM da-
ta.
Length Output 0.
The ASRC_CTL01.LENOUT0 bit field selects the serial output word length on
SRC0.
Serial Mode Output 0.
The ASRC_CTL01.SMODEOUT0 bit field selects the serial output format on SRC0.
Dither Enable 0.
The ASRC_CTL01.DITHER0 bit enables dithering before truncation on SRC0
when a word length less than 24 bits is selected.
Description/Enumeration
ASRC_CTL01 register should be at least one cycle before setting the
0 Matched phase slave disabled
1 Matched phase slave enabled
0 24 bits
1 20 bits
2 18 bits
3 16 bits
0 Left-justified
1 I2S
2 TDM
3 Right-justified
0 Truncation only
1 Dithering before truncation
ADSP-SC58x ASRC Register Descriptions
36–15