Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2889

• Attempts to change DMA_CFG.PSIZE of a receive operation (memory write) when the operation was not the
first work unit (with DMA_CFG.SYNC enabled)
Illegal Register Write During Run
The channel generates an error when a write occurs to writable registers of an enabled, running DMA channel. The
channel blocks the write. The DMA_STAT, DMA_BWLCNT, and
havior. The DMA_STAT
Address Alignment Error
The channel generates an address alignment error when any of the following apply:
• Alignment of a descriptor address is not on a 32-bit boundary.
• The current DMA_CFG.MSIZE configuration contains an unaligned transfer address. The
DMA_ADDRSTART
Memory Access Error
The channel generates a memory access error when the DMA process:
• attempts to access an unpopulated address,
• attempts to access an address defined as cache, or
• attempts to access a location that provokes a security violation
The error returned from the memory triggers the memory access error.
Trigger Overrun Error
A trigger overrun error is generated when a new trigger input occurred while an outstanding trigger is waiting. This
error is only generated if DMA_CFG.TOVEN is enabled.
Bandwidth-Monitor Error
The channel generates this error when the bandwidth-monitor count expires. This error is not fatal, and the DMA
channel continues operation.
Control Interface Error
The channel reports control-interface errors as bus errors to the bus master. This error can result from:
• An address error
• A register write error (write to a read-only register)
DMA Operating Modes
The DMA channel supports a number of different flow modes that control how the DMA channel progresses from
one work unit to the next.
The flow mode of a DMA channel is not a global setting. A DMA descriptor set can include the descriptor responsi-
ble for configuring the flow of the work unit. There is no restriction, limiting the flow configuration to be the same
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register is exempt from this behavior.
register is not aligned according to the DMA_CFG.MSIZE field.
DMA_BWMCNT registers are exempt from this be-
DMA Channel Errors
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