Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2685

Operating Modes and Options
These control signals can be internally generated or externally provided, as determined by the
SPORT_CTL_A.ICLK and SPORT_CTL_A.IFS bit settings, respectively.
Data and frame syncs can be sampled on the rising or falling edges of the SPORT clock signal, as determined by the
SPORT_CTL_A.CKRE bit. By default, the SPORT_CTL_A.CKRE = 0 setting configures the falling edge of the
SPORT_ACLK signal as the sampling edge for receive data and externally supplied frame syncs. The receive data
and frame syncs can be sampled on the rising edges of SPORT_ACLK when SPORT_CTL_A.CKRE = 1.
NOTE: The SPORT drives transmit data and internal frame sync signals on the opposite serial clock edge of the
sampling edge. Be sure to select the same value for SPORT_CTL_A.CKRE for transmit and receive func-
tions for any two HSPORTs that are connected together, and always verify the correct polarity for any
external device connected to the SPORT.
The Frame Sync and Data Driven on Rising Edge figure provides an example of the drive and sample edges when
two HSPORTs are connected together, each with SPORT_CTL_A.CKRE = 0. In this example, the HSPORT that
is configured as the transmitter drives the serial clock and frame sync signals, and both HSPORTs are configured for
early, active high frame syncs and a word length of eight bits.
Figure 34-3: Frame Sync and Data Driven on Rising Edge
The SCLK in the Frame Sync and Data Driven on Rising Edge figure is SCLK0_0.
NOTE:
As shown, the transmitting HSPORT provides the clock and generates the frame sync. Because the HSPORTs are
configured for early frame mode, the first bit of data is driven one serial clock later, with subsequent bits being driv-
en on the following rising clock edges in the signal train. When the receiving HSPORT samples the frame sync
signal (as indicated in the SAMPLED FS waveform), the SPORT_CTL_A.SLEN bit counter is loaded with the
SPORT_CTL_A.SLEN setting, after which each SPORT_ACLK decrements the SPORT_CTL_A.SLEN counter
until the full word is received. In this figure, the DRIVE FS and SAMPLED FS waveforms show the frame sync
required for the next word in a continuous data stream. Note that it is legal for this frame sync to be sampled syn-
chronous to the last bit of the previous data being sampled, as the early frame mode means that the data lags the
frame sync by one serial clock cycle. If the frame sync were sampled as asserted before the D0 bit is sampled, the
frame sync error is logged in the receiver's status register.
Since the transmitter drives the internally-generated frame sync and data on the rising edge of the serial clock, the
receiver must use the falling edge to sample the externally-supplied frame sync and data.
34–22
DRIVE
SCLK
DRIVE
FS
DRIVE
DATA D7 D6
SAMPLED
FS
SLEN
7 6
COUNTER
SAMPLED
D7 D6
DATA
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
D5 D4 D3 D2 D1
5 4 3 2
D5 D4 D3 D2
D0
1 0
D1 D0