Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2747

ADSP-SC58x SPORT Register Descriptions
Table 34-31: SPORT_MCTL_A Register Fields (Continued)
Bit No.
(Access)
2 MCPDE
(R/W)
0 MCE
(R/W)
34–84
Bit Name
Multichannel Packing DMA Enable.
The SPORT_MCTL_A.MCPDE bit enables DMA data packing for transmit and ena-
bles DMA data unpacking for the half SPORT's multichannel data transfers.
Multichannel enable.
The SPORT_MCTL_A.MCE bit enables multichannel operations for the half SPORT.
The half SPORT is configured in normal multichannel mode if
SPORT_CTL_A.OPMODE=0; while it is configured in packed mode if
SPORT_CTL_A.OPMODE=1. When configuring in these modes, the multichannel
enable bit (SPORT_MCTL_A.MCE) should be set before enabling the SPORT data
channel enable bits (SPORT_CTL_A.SPENPRI and/or
SPORT_CTL_A.SPENSEC). When these channel bits transition from 1 to 0, note
that the half SPORT's data transfer buffers are cleared, and the
SPORT_CTL_A.DERRPRI and SPORT_CTL_A.DERRSEC bits are cleared.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 Disable
1 Enable
0 Disable
1 Enable