Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2875

For descriptor sets containing only a single descriptor, the transfer takes place as a single 32-bit transfer. For descrip-
tor sets containing multiple descriptors, the DMA engine fetches each 32-bit descriptor individually and treats it as
multiple 32-bit transfers.
DMA Channel Peripheral DMA Bus
The DMA channel connects to peripherals or other DMA channels through the peripheral DMA bus. This bus is a
dedicated point-to-point interface supporting data bus widths of 8, 16, 32, or 64 bits. The data bus widths for a
given DMA channel on a particular processor can vary and are not configurable. Reading the DMA_STAT.PBWID
field permits determining the assigned bus width.
The DMA channel operates at one of the SCLKn frequencies, as does the peripheral DMA bus. The Peripheral
DMA Bus Signals table provides descriptions of the peripheral DMA bus signals.
Table 38-6: Peripheral DMA Bus Signals
Signal
PDMA_WRITE_DATA
PDMA_READ_DATA
PDMA_DMA_GRANT
PDMA_CMD
PDMA_CTRL
Peripheral Control Commands
The peripheral DMA bus of the DMA channel provides a means for peripherals on the processor to issue commands
to the DMA channel. These commands provide greater control over the DMA channel operation. This control im-
proves real-time performance and relieves control and interrupt demands on the core. Peripherals can send com-
mands to the DMA controller over the 3-bit PERI_CMD bus. The DMA control commands extend the set of oper-
ations available to the peripheral beyond the simple "request data" command used by peripherals in general. Refer to
the appropriate peripheral chapter for a description on how that peripheral uses DMA control commands.
These DMA control commands (see the PDMA_CMD Peripheral DMA Control Commands table) are not visible
to or controlled by the program. But, their use by a peripheral has implications for the structure of the DMA trans-
fers that the peripheral can support. It is important to write application software such that it complies with certain
restrictions, regarding work units and descriptor chains. Complying with this guideline makes the peripheral operate
properly whenever it issues DMA control commands.
The PDMA_CMD Peripheral DMA Control Commands table describes the commands the DMA controller issues.
The following sections describe these commands in more detail.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Width (bits)
8, 16, 32, or 64
8, 16, 32, or 64
3
Description
Data bus used for write operations. The width of the bus can be deter-
mined from DMA_STAT.PBWID.
Data bus used for read operations. The width of the bus can be deter-
mined from DMA_STAT.PBWID.
Control signals to indicate that data is valid for DMA channel read opera-
tions (peripheral transmit). These signals indicate that the DMA channel
is ready to receive data for write operations (peripheral receive).
The peripheral uses the signal for issuing DMA channel control com-
mands.
The peripheral uses the control signals to send various commands to the
DMA channel and control the direction of flow.
Architectural Concepts
38–11