Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2885

CAUTION: Disabling the channel with the DMA_CFG.EN bit while data transfers are in-progress causes the loss
of the data in the FIFO.
A synchronized transition configuration directs the channel to drain the DMA FIFO to the destination memory or
peripheral. This FIFO operation occurs before the channel signals any interrupt and before the channel fetches any
subsequent descriptor or data. This operation incurs greater latency, but provides direct synchronization between the
DMA interrupt and the state of the data at the peripheral.
If the configuration enables synchronization and enables interrupts, on the last descriptor in a work unit, the inter-
rupt occurs when the channel transfers the final data to the peripheral. This event allows the service routine to
switch properly to non-DMA transmit operation. When the event vectors to the interrupt service routine, the DMA
channel FIFO is empty, and the DMA channel is no longer running (indicated by the DMA_STAT.RUN bits).
A synchronized transition also allows greater flexibility in the format of the DMA descriptor chain. When enabled,
the next descriptor can have any DMA_CFG.PSIZE configuration or read/write direction supported by the periph-
eral and can come from either memory space (internal or external). This feature can be useful in managing MDMA
work unit queues, since it is no longer necessary to interrupt the queue between dissimilar work units.
Work Unit Receive and MDMA Destination Transitions
In DMA receive channels (memory write operations), the DMA_CFG.SYNC bit controls the handling of the DMA
FIFO between descriptor chains (not individual descriptor sets), during the DMA channel pause. The DMA chan-
nel pauses after the descriptor sets configured with stop flow mode are complete. Restart the channel (for example,
after an interrupt) by writing the
the configuration disables synchronization in the
continuous transition. In this mode, the DMA FIFO retains any data items received during the channel pause, and
they are the first items written to memory in the new work unit. This mode of operation provides lower latency at
work unit transitions and ensures no dropping of data items during a DMA pause. The channel provides this opera-
tion at the cost of certain restrictions on the DMA descriptors.
NOTE: If the DMA_CFG.SYNC bit disables synchronization on the first descriptor of a chain after a DMA pause,
do not change the configuration of the DMA_CFG.PSIZE field of the new chain from the previous de-
scriptor chain (active before the pause). This restriction applies unless the DMA channel is reset between
chains by disabling and then re-enabling the DMA channel.
If the DMA_CFG.SYNC bit configuration enables synchronization, the channel uses a synchronized transition. In
this mode, only the data that the DMA channel receives from the peripheral after the write to the
ter gets to memory. The channel discards any prior data items transferred from the peripheral to the DMA FIFO
before this register write occurs. This operation provides direct synchronization between the data stream received
from the peripheral and the timing of the channel restart, which occurs on the write to the
For receive DMA operations, the synchronization has no effect in transitions between work units in the same de-
scriptor chain. When the flow mode of previous descriptor was not stopped, the DMA channel did not pause.
If a descriptor chain begins with synchronization enabled, there is no restriction on the DMA_CFG.PSIZE of the
new chain in comparison with the previous chain.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DMA_CFG register of the channel with a value that enables the DMA channel. If
DMA_CFG value of the new work unit, the configuration selects a
Work Unit Transition Flow
DMA_CFG regis-
DMA_CFG register.
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