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Low-power universal asynchronous receiver transmitter (LPUART)
34.7.6
LPUART request register (LPUART_RQR)
Address offset: 0x18
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:5 Reserved, must be kept at reset value.
Bit 4 TXFRQ: Transmit data flush request
Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in
Bit 3 RXFRQ: Receive data flush request
Bit 2 MMRQ: Mute mode request
Bit 1 SBKRQ: Send break request
Note: If the application needs to send the break character following all previously inserted
Bit 0 Reserved, must be kept at reset value.
34.7.7
LPUART interrupt and status register (LPUART_ISR)
Address offset: 0x1C
Reset value: 0x0080 00C0
The same register can be used in FIFO mode enabled (this section) and FIFO mode
disabled (next section).
FIFO mode enabled
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
1142/1306
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit is used when FIFO mode is enabled. TXFRQ bit is set to flush the whole FIFO. This
sets the flag TXFE (TXFIFO empty, bit 23 in the LPUART_ISR register).
order to ensure that no data are written in the data register.
Writing 1 to this bit clears the RXNE flag.
This enables discarding the received data without reading it, and avoid an overrun condition.
Writing 1 to this bit puts the LPUART in Mute mode and resets the RWU flag.
Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as
the transmit machine is available.
data, including the ones not yet transmitted, the software should wait for the TXE flag
assertion before setting the SBKRQ bit.
28
27
26
25
TXFT
RXFT
Res.
r
r
12
11
10
9
Res.
CTS
CTSIF
r
r
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
RXFF
TXFE
REACK TEACK
r
r
r
8
7
6
Res.
TXFNF
TC
RXFNE
r
r
RM0461 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
TXFRQ RXFRQ MMRQ SBKRQ
w
w
w
21
20
19
18
WUF
RWU
SBKF
r
r
r
r
5
4
3
2
IDLE
ORE
NE
r
r
r
r
RM0461
17
16
Res.
Res.
1
0
Res.
w
17
16
CMF
BUSY
r
r
1
0
FE
PE
r
r
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