Table 255. Dp Register Map And Reset Values - STMicroelectronics STM32WLEx Reference Manual

RM0461
36.4.11 DP register map and reset values
These registers are not on the CPU memory bus and are only accessed through SW-DP
and JTAG-DP debug interface.
The debug port address is 2-bit wide, defined in the JTAG-DP register DPACC or SW-DP
packet request A[3:2] field.
Offset Register name
DP_DPIDR
0x00
Reset value
DP_ABORTR
0x00
Reset value
DP_CTRLSTATR
(1)
0x04
Reset value
DP_DLCR
(2)
0x04
Reset value
DP_TARGETIDR
(3)
0x04
Reset value
DP_DLPIDR
(4)
0x04
Reset value
DP_RESENDR
0x08
Reset value

Table 255. DP register map and reset values

PARTNO[7:0]
0 1 0 1 1 0 1 1 1
0 0 0
0 0 0 0 0 1 0 0 1
0 0 0 0
0 0 0 0 0 0 0 0 0
0 1 0 0 0 0
TRNCNT[11:0]
0 0 0 0 0 0 0 0 0
TPARTNO[15:0]
0 0 1 0 1 1 1 0 0
RESEND[31:0]
0 0 0 0 0 0 0 0 0
RM0461 Rev 5
Debug support (DBG)
DESIGNER[10:0]
1 0 0 1 0 0 0 1 1
0 0 0 0 0 0 0 0 0
0 0
TDESIGNER[10:0]
0 0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 0 0
1 0 1 1
0 0 0 0 0
0 0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0 0
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