STMicroelectronics STM32WLEx Reference Manual page 1213

RM0461
36 Debug support (DBG)
36.1 DBG introduction and main features
A comprehensive set of debug features is provided to support software development and
system integration:
•
Breakpoint debugging of the CPU core in the system
•
Code execution tracing
•
Software instrumentation
The debug features can be controlled via a JTAG/Serial-wire debug access port, using
industry standard debugging tools. A trace port allows data to be captured for logging and
analysis.
The debug features are based on Arm CoreSight™ components.
• General features:
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•
CPU debug features
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CPU debug features are accessible by the debugger via the CPU AHB-AP.
Additional information can be found in the Arm
Device level debug features are controlled in the DBGMCU (see
36.2 DBG use cases
The trace and debug system is designed to support a variety of typical use cases:
•
Low-cost trace
Limited trace capability is available over the single-wire debug output. This supports
code instrumentation using printf, tracing of data and address watchpoints, interrupt
detection and program counter sampling. Single-wire trace can be maintained even
when the processor is switched off or clock-stopped.
•
Breakpoint debugging of the core
The processor core can be debugged using equipment connected to the JTAG/SWD
debug port. This enables, among others, breakpoint and watchpoint setting, code
stepping and memory access.
• Tracing code execution via the trace port
Trace information from the CPU (Cortex-M4) is combined into a single trace stream
and sent to a trace port analyzer in real time. An ID embedded in the trace allows the
analyzer to identify the source of each information packet.
SWJ-DP: JTAG/Serial-wire debug port
AHB-AP: AHB access port
ROM table (see Section
System control space (SCS)
Breakpoint unit (FPB) (see
Data watchpoint and trace unit (DWT) (see
Instrumentation trace macrocell (ITM) (see
Trace port interface unit (TPIU) (see
36.7)
Section 36.8)
Section
Section
Section
®
documents referenced in
RM0461 Rev 5
Debug support (DBG)
36.6)
36.9)
36.10)
Section
Section 36.11).
36.12.
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