STMicroelectronics STM32WLEx Reference Manual page 1209

RM0461
Bit 12 ASTRTEN: Asynchronous start enable.
0: The Asynchronous start is disabled.
When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is
received and an appropriate transition is detected on the WS signal.
1: The Asynchronous start is enabled.
When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is
received and the appropriate level is detected on the WS signal.
Note: The appropriate transition is a falling edge on WS signal when I
or a rising edge for other standards.
The appropriate level is a low level on WS signal when I
level for other standards.
Please refer to
Bit 11 I2SMOD: I2S mode selection
0: SPI mode is selected
1: I2S mode is selected
Note: This bit should be configured when the SPI is disabled.
Bit 10 I2SE: I2S enable
0: I2S peripheral is disabled
1: I2S peripheral is enabled
Note: This bit is not used in SPI mode.
Bits 9:8 I2SCFG[1:0]: I2S configuration mode
00: Slave - transmit
01: Slave - receive
10: Master - transmit
11: Master - receive
Note: These bits should be configured when the I2S is disabled.
They are not used in SPI mode.
Bit 7 PCMSYNC: PCM frame synchronization
0: Short frame synchronization
1: Long frame synchronization
Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used).
It is not used in SPI mode.
Bit 6 Reserved, must be kept at reset value.
Bits 5:4 I2SSTD[1:0]: I2S standard selection
2
00: I S Philips standard
01: MSB justified standard (left justified)
10: LSB justified standard (right justified)
11: PCM standard
For more details on I
Note: For correct operation, these bits should be configured when the I2S is disabled.
They are not used in SPI mode.
Serial peripheral interface / integrated interchip sound (SPI/I2S)
Section 35.7.3: Start-up description
2
S standards, refer to Section 35.7.2 on page 1183
RM0461 Rev 5
2
S Philips Standard is used,
2
S Philips Standard is used, or a high
for additional information.
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