Figure 367. Start Sequence In Master Mode - STMicroelectronics STM32WLEx Reference Manual

RM0461
WS (O)
CK (O),
CKPOL = 0
CK (O),
CKPOL = 1
SD (O)
I2SE
WS (O)
CK (O),
CKPOL = 0
CK (O),
CKPOL = 1
SD (O)
I2SE
WS (O)
CK (O),
CKPOL = 0
CK (O),
CKPOL = 1
SD (O)
I2SE
WS (O)
CK (O),
CKPOL = 0
CK (O),
CKPOL = 1
SD (O)
I2SE
dum: not significant data
In slave mode, the way the frame synchronization is detected, depends on the value of
ASTRTEN bit.
If ASTRTEN = 0, when the audio interface is enabled (I2SE = 1), then the hardware waits for
the appropriate transition on the incoming WS signal, using the CK signal.
Serial peripheral interface / integrated interchip sound (SPI/I2S)

Figure 367. Start sequence in master mode

Master I2S Philips Standard
dum Left sample
Master I2S MSB or LSB justified
Left sample
dum
Master PCM short frame
dum Sample1
Master PCM long frame
dum Sample1
RM0461 Rev 5
Right sample
Right sample
Sample 2
Sample 2
MSv37520V2
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