Table 248. Jtag/Serial-Wire Debug Port Pins; Table 249. Single-Wire Trace Port Pins; Figure 370. Block Diagram Of Debug Support Infrastructure - STMicroelectronics STM32WLEx Reference Manual

Debug support (DBG)
36.3 DBG functional description
36.3.1 DBG block diagram

Figure 370. Block diagram of debug support infrastructure

JTAG/Serial-wire port
JTMS/SWDIO
JTDI
JTDO
JTCK/SWCLK
nJTRST
36.3.2 DBG pins and internal signals
Pin name
JTMS/SWDIO
JTCK/SWCLK
JTDI
(1)
JTDO/TRACESWO
nJTRST
1. Debug access port JTDO and Trace port TRACESWO are multiplexed on a single device GPIO pin.
Pin name Type
TRACESWO O
1. TRACESWO is multiplexed with JTDO. This means that single-wire trace is only available when using the Serial-wire
debug interface, and not when using JTAG.
36.3.3 DBG reset and clocks
The debug port (SWJ-DP) is reset by a power-on reset or an OBL (option byte loading)
reset, and when waking up from Standby mode.
The debugger supplies the clock for the debug port via the debug interface pin
JTCK/SWCLK. This clock is used to register the serial input data in both Serial-wire and
JTAG modes, as well as to operate the state machines and internal logic of the debug port.
1214/1306
Debug access
port (DAP)
SWJ-DP
(1)

Table 248. JTAG/Serial-wire debug port pins

JTAG debug port
Type Description
I JTAG test mode select
I JTAG test clock
I JTAG test data input
O JTAG test data output
I JTAG test reset

Table 249. Single-wire trace port pins

Single wire trace asynchronous data out
(1)
DWT FPB
AHB
Core
PPB
CPU
Cortex-M4
(1) Arm CoreSight components
Serial-wire debug port
Type Description
IO Serial wire data in/out
I Serial wire clock
-
-
-
Description
RM0461 Rev 5
(1) (1) (1)
ITM TPIU
ROM
(1)
table
Pin assignment
-
-
-
Pin assignment
RM0461
Trace port
TRACESWO
DBG_MCU
MSv60365V1
PA13
PA14
PA15
PB3
PB4
(1)
PB3