STMicroelectronics STM32WLEx Reference Manual page 1223

RM0461
Bit 3 WDERRCLR: write data error clear
0: No effect
1: Clears DP_CTRLSTATR.WDATAERR bit.
Bit 2 STKERRCLR: sticky error clear
0: No effect
1: Clears DP_CTRLSTATR.STICKYERR bit.
Bit 1 STKCMPCLR: sticky compare clear
0: No effect
1: Clears DP_CTRLSTATR.STICKYCMP bit
Bit 0 DAPABORT: data AP abort
Aborts current AP transaction if an excessive number of WAIT responses are returned,
indicating that the transaction is stalled.
0: No effect
1: Aborts the transaction.
36.4.3 DP control and status register (DP_CTRLSTATR)
Address offset: 0x04
and DP_SELECTR.DPBANKSEL = 0
Reset value: 0x0000 0000
31 30 29
CDBG CDBG
Res. Res. PWRU PWRU
PACK PREQ
r
15 14 13
TRNCNT[3:0]
r r r
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 CDBGPWRUPACK: see description in
0 = DAPCLK gated
1 = DAPCLK enabled
Bit 28 CDBGPWRUPREQ: control of DAPCLK enable request signal
0 = Requests DAPCLK gating
1 = Requests DAPCLK enabled
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:12 TRNCNT[11:0]: transaction counter
To program a sequence of transactions to incremental addresses via an AP, TRNCNT is
loaded with the number of transactions to perform. It is decremented at the successful
completion of each transaction.
28 27 26 25
Res. Res. Res.
r
12 11 10 9
MASKLANE[3:0]
r r r r
24 23 22
Res.
r r
8 7 6
WDATA READ STICK
ERR OK YERR
r r r rc_w1
Section 36.3.6
RM0461 Rev 5
Debug support (DBG)
21 20 19 18
TRNCNT[11:4]
r r r r
5 4 3 2
STICK
TRNMODE[1:0]
YCMP
rc_w1 r r
17 16
r r
1 0
STICK ORUN
YORU DETEC
N T
rc_w1 r
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