STMicroelectronics STM32WLEx Reference Manual page 1193

RM0461
Figure 369
by the reset and clock controller (RCC) of the product. The I2SxCLK clock can be
asynchronous with respect to the SPI/I2S APB clock.
Warning:
The audio sampling frequency may be 192 kHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz,
22.05 kHz, 16 kHz, 11.025 kHz or 8 kHz (or any other value within this range).
In order to reach the desired frequency, the linear divider needs to be programmed
according to the formulas below:
2
For I S modes:
When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):
When the master clock is disabled (MCKOE bit cleared):
CHLEN = 0 when the channel frame is 16-bit wide and,
CHLEN = 1 when the channel frame is 32-bit wide.
For PCM modes:
When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):
When the master clock is disabled (MCKOE bit cleared):
CHLEN = 0 when the channel frame is 16-bit wide and,
CHLEN = 1 when the channel frame is 32-bit wide.
Where F
provided to the SPI/I2S block.
Serial peripheral interface / integrated interchip sound (SPI/I2S)
presents the communication clock architecture. The I2SxCLK clock is provided
In addition, it is mandatory to keep the I2SxCLK frequency
higher or equal to the APB clock used by the SPI/I2S block. If
this condition is not respected the SPI/I2S does not work
properly.
Fs
=
Fs
= ----------------------------------------------------------------------------------------------------------------------------------------------------------------- -
× (
32 CHLEN
Fs
=
Fs
= ----------------------------------------------------------------------------------------------------------------------------------------------------------------- -
× (
16 CHLEN
is the audio sampling frequency, and F
S
F
I2SxCLK
---------------------------------------------------------------------------------------------------------- -
× ( 2 ( × I2SDIV )
256
F
I2SxCLK
1 ) × ( 2 (
+
F
I2SxCLK
---------------------------------------------------------------------------------------------------------- -
× ( 2 ( × I2SDIV )
128
F
I2SxCLK
1 ) × ( 2 (
+
I2SxCLK
RM0461 Rev 5
ODD )
+
× I2SDIV ) ODD )
+
ODD )
+
× I2SDIV ) ODD )
+
is the frequency of the kernel clock
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