Nor/Psram Address Mapping; Nand Flash Memory Address Mapping; Table 40. Nor/Psram Bank Selection; Table 41. Nor/Psram External Memory Address - ST STM32F446 Series Reference Manual

RM0390
11.4.1

NOR/PSRAM address mapping

HADDR[27:26] bits are used to select one of the four memory banks as shown in
1. HADDR are internal AHB address lines that are translated to external memory.
The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte
address whereas the memory is addressed at word level, the address actually issued to the
memory varies according to the memory data width, as shown in the following table.
Memory width
8-bit
16-bit
1. In case of a 16-bit external memory width, the FMC will internally use HADDR[25:1] to generate the
address for external memory FMC_A[24:0].
Whatever the external memory width, FMC_A[0] should be connected to external memory address A[0].
11.4.2

NAND Flash memory address mapping

The NAND bank is divided into memory areas as indicated in
Start address
0x8800 0000
0x8000 0000
For NAND Flash memory, the common and attribute memory spaces are subdivided into
three sections (see in
•
Data section (first 64 Kbytes in the common/attribute memory space)
•
Command section (second 64 Kbytes in the common / attribute memory space)
•
Address section (next 128 Kbytes in the common / attribute memory space)

Table 40. NOR/PSRAM bank selection

(1)
HADDR[27:26]
00
01
10
11

Table 41. NOR/PSRAM External memory address

(1)
Data address issued to the memory
HADDR[25:0]
HADDR[25:1] >> 1

Table 42. NAND memory mapping and timing registers

End address
0x8BFF FFFF
Bank 3 - NAND Flash
0x83FF FFFF
Table 43 below) located in the lower 256 Kbytes:
RM0390 Rev 4
Flexible memory controller (FMC)
Bank 1 - NOR/PSRAM 1
Bank 1 - NOR/PSRAM 2
Bank 1 - NOR/PSRAM 3
Bank 1 - NOR/PSRAM 4
FMC bank Memory space
Attribute
Common
Selected bank
Maximum memory capacity (bits)
64 Mbytes x 8 = 512 Mbit
64 Mbytes/2 x 16 = 512 Mbit
Table 42.
Timing register
FMC_PATT (0x8C)
FMC_PMEM (0x88)
Table 40.
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