ST STM32F446 Series Reference Manual page 119

RM0390
otherwise TIMxCLK = 2x PCLKx.
3. When TIMPRE bit in the RCC_DCKCFGR register is set, if APBx prescaler is 1,2 or 4, then TIMxCLK =
HCLK, otherwise TIMxCLK = 4x PCLKx.
The clock controller provides a high degree of flexibility to the application in the choice of the
external crystal or the oscillator to run the core and peripherals at the highest frequency
and, guarantee the appropriate frequency for peripherals that need a specific clock like USB
OTG FS and HS, I2S, SAI, and SDIO.
Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2)
and the low-speed APB (APB1) domains. The maximum frequency of the AHB domain is
180 MHz. The maximum allowed frequency of the high-speed APB2 domain is 90 MHz. The
maximum allowed frequency of the low-speed APB1 domain is 45 MHz
All peripheral clocks are derived from the system clock (SYSCLK) except for:
•
The USB OTG FS clock (48 MHz), which is coming from a specific output of the PLL
(PLLP) or PLLSAI (PLLSAIP)
• The SDIO clock (48 MHz) which is coming from a specific output of the PLL48CLK
(PLLQ, PLLSAIP), or System Clock.
•
I2S1/2 clocks
To achieve high-quality audio performance and for a better configuration flexibility, the
I2S1 clock and I2S2 clock (which are respectively clocks for I2Ss mapped on APB1
and APB2) can be derived from four sources: specific main PLL output, a specific
PLLI2S output, from an external clock mapped on the I2S_CKIN pin or from HSI/HSE
•
SAIs clock
The SAI1/SAI2 clocks are generated from a specific PLL (Main PLL, PLLSAI, or
PLLI2S), from an external clock mapped on the I2S_CKIN pin or from HSI/HSE clock.
The PLLSAI can be used as clock source for SAI1 peripheral in case the PLLI2S is
programmed to achieve another audio sampling frequency (49.152 MHz or
11.2896 MHz), and the application requires both frequencies at the same time.
•
The USB OTG HS (60 MHz) clock which is provided from the external PHY.
•
SPDIF-Rx clock
The SPDIF-Rx clock is generated from a specific output of PLLI2S or from a specific
output of main PLL.
• HDMI-CEC clock which is generated from LSE or HSI divided by 488.
•
FMPI2C1 clock which can also be generated from HSI, SYSCLK or APB1 clock.
The timer clock frequencies are automatically set by hardware. There are two cases
depending on the value of TIMPRE bit in RCC_CFGR register:
• If TIMPRE bit in RCC_DKCFGR register is reset:
If the APB prescaler is configured to a division factor of 1, the timer clock frequencies
(TIMxCLK) are set to PCLKx. Otherwise, the timer clock frequencies are twice the
frequency of the APB domain to which the timers are connected: TIMxCLK = 2xPCLKx.
•
If TIMPRE bit in RCC_DKCFGR register is set:
If the APB prescaler is configured to a division factor of 1, 2 or 4, the timer clock
frequencies (TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies is four
times the frequency of the APB domain to which the timers are connected: TIMxCLK =
4xPCLKx.
RM0390 Rev 4
Reset and clock control (RCC)
119/1328
175