Configuration Register 2 (Sai_Acr2 / Sai_Bcr2) - ST STM32F446 Series Reference Manual

Serial audio interface (SAI)
Bit 4 Reserved, must be kept at reset value.
Bits 3:2 PRTCFG[1:0]: Protocol configuration
These bits are set and cleared by software. These bits have to be configured when the audio block is
disabled.
00: Free protocol. Free protocol allows to use the powerful configuration of the audio block to
address a specific audio protocol (such as I2S, LSB/MSB justified, TDM, PCM/DSP...) by setting
most of the configuration register bits as well as frame configuration register.
01: SPDIF protocol
10: AC'97 protocol
11: Reserved
Bits 1:0 MODE[1:0]: SAIx audio block mode
These bits are set and cleared by software. They must be configured when SAIx audio block is
disabled.
00: Master transmitter
01: Master receiver
10: Slave transmitter
11: Slave receiver
Note: When the audio block is configured in SPDIF mode, the master transmitter mode is forced
(MODE[1:0] = 00). In Master transmitter mode, the audio block starts generating the FS and the
clocks immediately.
28.5.3

Configuration register 2 (SAI_ACR2 / SAI_BCR2)

Address offset: Block A: 0x008
Address offset: Block B: 0x028
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
COMP[1:0] CPL
rw rw rw
962/1328
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
MUTECNT[5:0]
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24 23 22 21
Res. Res. Res. Res.
8 7 6 5
MUTE
MUTE
VAL
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RM0390 Rev 4
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
F
TRIS FTH[2:0]
FLUSH
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RM0390
16
Res.
0
rw