Tim9 To Tim14 Functional Description; Time-Base Unit; Counter Enable Bit (Cen) In Timx_Cr1 Register Is Set (Refer Also To The Slave Mode Controller; Description To Get More Details On Counter Enabling) - ST STM32F446 Series Reference Manual

Advanced arm-based 32-bit mcus

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TIM9 to TIM14 functional description

The main block of the timer is a 16-bit counter with its related auto-reload register. The

counters counts up.

The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by

software. This is true even when the counter is running.

The time-base unit includes:

Counter register (TIMx_CNT)

Prescaler register (TIMx_PSC)

Auto-reload register (TIMx_ARR)

The auto-reload register is preloaded. Writing to or reading from the auto-reload register

accesses the preload register. The content of the preload register are transferred into the

shadow register permanently or at each update event (UEV), depending on the auto-reload

preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter

reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be

generated by software. The generation of the update event is described in details for each

configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the

Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It

is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).

It can be changed on the fly as this control register is buffered. The new prescaler ratio is

taken into account at the next update event.

RM0390 Rev 4

General-purpose timers (TIM9 to TIM14)

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