Timer Synchronization (Tim9/12); Debug Mode; Tim9 And Tim12 Registers; Tim9/12 Control Register 1 (Timx_Cr1) - ST STM32F446 Series Reference Manual

RM0390
18.3.12

Timer synchronization (TIM9/12)

The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 17.3.15: Timer synchronization
18.3.13

Debug mode

When the microcontroller enters debug mode (Cortex
counter either continues to work normally or stops, depending on DBG_TIMx_STOP
configuration bit in DBG module. For more details, refer to
for timers, watchdog, bxCAN and
18.4

TIM9 and TIM12 registers

Refer to
The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read
accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
18.4.1

TIM9/12 control register 1 (TIMx_CR1)

Address offset: 0x00
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 CKD: Clock division
Bit 7 ARPE: Auto-reload preload enable
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One-pulse mode
Section 1.1 on page 51
12 11 10 9
Res. Res. CKD[1:0]
rw
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (TIx),
00: t = t
DTS CK_INT
01: t = 2 × t
DTS CK_INT
10: t = 4 × t
DTS CK_INT
11: Reserved
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
0: Counter is not stopped on the update event
1: Counter stops counting on the next update event (clearing the CEN bit).
General-purpose timers (TIM9 to TIM14)
for details.
®
I2C.
for a list of abbreviations used in register descriptions.
8 7 6
ARPE Res.
rw rw
RM0390 Rev 4
-M4 with FPU core halted), the TIMx
Section 33.16.2: Debug support
5 4 3 2
Res. Res. OPM URS
rw rw
1 0
UDIS CEN
rw rw
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