User Manuals: ST RM0390 STM32F446xx microcontrollers

Manuals and User Guides for ST RM0390 STM32F446xx microcontrollers. We have 1 ST RM0390 STM32F446xx microcontrollers manual available for free PDF download: Reference Manual

ST RM0390 Reference Manual

ST RM0390 Reference Manual (1328 pages)

advanced Arm-based 32-bit MCUs

Brand: ST | Category: Microcontrollers | Size: 16 MB

Table of Contents

Table of Contents

2
Independent Trigger Without Wave Generation

409
Clock Selection

465
Figure 159. Counter Timing Diagram with Prescaler Division Change from 1 to 2

523
- Counter Modes
  524
- Figure 160. Counter Timing Diagram with Prescaler Division Change from 1 to 4
  524
- Figure 161. Counter Timing Diagram, Internal Clock Divided by 1
  525
- Figure 162. Counter Timing Diagram, Internal Clock Divided by 2
  525
- Figure 163. Counter Timing Diagram, Internal Clock Divided by 4
  525
- Figure 164. Counter Timing Diagram, Internal Clock Divided by N
  526
- Figure 165. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
  526
- Figure 166. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
  527
- Figure 167. Counter Timing Diagram, Internal Clock Divided by 1
  528
- Figure 168. Counter Timing Diagram, Internal Clock Divided by 2
  528
- Figure 169. Counter Timing Diagram, Internal Clock Divided by 4
  528
- Figure 170. Counter Timing Diagram, Internal Clock Divided by N
  529
- Figure 171. Counter Timing Diagram, Update Event
  529
- Figure 172. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
  530
- Figure 173. Counter Timing Diagram, Internal Clock Divided by 2
  531
- Figure 174. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
  531
- Figure 175. Counter Timing Diagram, Internal Clock Divided by N
  531
- Figure 176. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
  532
- Figure 177. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
  532
- Clock Selection
  533
- Figure 178
  533
- Figure 178. Control Circuit in Normal Mode, Internal Clock Divided by 1
  533
- For more Details
  533
- Internal Clock Source (CK_INT)
  533
- Without Prescaler
  533
- Figure 179. TI2 External Clock Connection Example
  534
- Figure 180. Control Circuit in External Clock Mode 1
  535
- Figure 181. External Trigger Input Block
  535
- Capture/Compare Channels
  536
- Figure 182. Control Circuit in External Clock Mode 2
  536
- Figure 183. Capture/Compare Channel (Example: Channel 1 Input Stage)
  537
- Figure 184. Capture/Compare Channel 1 Main Circuit
  537
- Figure 185. Output Stage of Capture/Compare Channel (Channel 1)
  538
- Input Capture Mode
  538
- PWM Input Mode
  539
- Figure 186. PWM Input Mode Timing
  540
- Forced Output Mode
  540
- Output Compare Mode
  541
- Figure 187. Output Compare Mode, Toggle on OC1
  542
- PWM Mode
  542
- Figure 188. Edge-Aligned PWM Waveforms (ARR=8)
  543
- Figure 189. Center-Aligned PWM Waveforms (ARR=8)
  544
- Figure 190. Example of One-Pulse Mode
  545
- One-Pulse Mode
  545
- Clearing the Ocxref Signal on an External Event
  546
- Encoder Interface Mode
  547
- Figure 191. Clearing Timx Ocxref
  547
- Table 111. Counting Direction Versus Encoder Signals
  548
- Figure 192. Example of Counter Operation in Encoder Interface Mode
  549
- Figure 193. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
  549
- Figure 194. Control Circuit in Reset Mode
  550
- Timer Input XOR Function
  550
- Timers and External Trigger Synchronization
  550
- Figure 195. Control Circuit in Gated Mode
  551
- Figure 196. Control Circuit in Trigger Mode
  552
- Figure 197. Control Circuit in External Clock Mode 2 + Trigger Mode
  553
- Figure 198. Master/Slave Timer Example
  553
- Timer Synchronization
  553
- Figure 199. Gating Timer 2 with OC1REF of Timer 1
  554
- Figure 200. Gating Timer 2 with Enable of Timer 1
  555
- Figure 201. Triggering Timer 2 with Update of Timer 1
  556
- Figure 202. Triggering Timer 2 with Enable of Timer 1
  557
- Debug Mode
  558
- Figure 203. Triggering Timer 1 and 2 with Timer 1 TI1 Input
  558
- TIM2 to TIM5 Registers
  559
- Timx Control Register 1 (Timx_Cr1)
  559
- Timx Control Register 2 (Timx_Cr2)
  561
- Timx Slave Mode Control Register (Timx_Smcr)
  562
- Table 112. Timx Internal Trigger Connections
  563
- Timx Dma/Interrupt Enable Register (Timx_Dier)
  564
- Timx Status Register (Timx_Sr)
  565
- Timx Event Generation Register (Timx_Egr)
  567
- Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
  568
- Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
  571
- Timx Capture/Compare Enable Register (Timx_Ccer)
  572
- Table 113. Output Control Bit for Standard Ocx Channels
  573
- Timx Auto-Reload Register (Timx_Arr)
  574
- Timx Counter (Timx_Cnt)
  574
- Timx Prescaler (Timx_Psc)
  574
- Timx Capture/Compare Register 1 (Timx_Ccr1)
  575
- Timx Capture/Compare Register 2 (Timx_Ccr2)
  575
- Timx Capture/Compare Register 3 (Timx_Ccr3)
  576
- Timx Capture/Compare Register 4 (Timx_Ccr4)
  576
- Timx DMA Address for Full Transfer (Timx_Dmar)
  577
- Timx DMA Control Register (Timx_Dcr)
  577
- TIM2 Option Register (TIM2_OR)
  578
- TIM5 Option Register (TIM5_OR)
  579
- Table 114. TIM2 to TIM5 Register Map and Reset Values
  580
- Timx Register Map
  580
- General-Purpose Timers (TIM9 to TIM14)
  582
- TIM9 to TIM14 Introduction
  582
- TIM9 to TIM14 Main Features
  582
- TIM9/TIM12 Main Features
  582
- Auto-Reload Register (Timx_Arr)
  583
- Figure 204. General-Purpose Timer Block Diagram (TIM9 and TIM12)
  583
- TIM10/TIM11 and TIM13/TIM14 Main Features
  583
- Figure 205. General-Purpose Timer Block Diagram (TIM10/11/13/14)
  584
- Counter Enable Bit (CEN) in Timx_Cr1 Register Is Set (Refer also to the Slave Mode Controller
  585
- Description to Get more Details on Counter Enabling)
  585
- Give some Examples of the Counter Behavior When the Prescaler
  585
- Prescaler Description
  585
- Ratio Is Changed on the Fly
  585
- TIM9 to TIM14 Functional Description
  585
- Time-Base Unit
  585
- Figure 206. Counter Timing Diagram with Prescaler Division Change from 1 to 2
  586
- Figure 207. Counter Timing Diagram with Prescaler Division Change from 1 to 4
  586
- Counter Modes
  587
- Figure 208. Counter Timing Diagram, Internal Clock Divided by 1
  587
- Figure 209. Counter Timing Diagram, Internal Clock Divided by 2
  588
- Figure 210. Counter Timing Diagram, Internal Clock Divided by 4
  588
- Figure 211. Counter Timing Diagram, Internal Clock Divided by N
  588
- Figure 212. Counter Timing Diagram, Update Event When ARPE=0
  589
- Figure 213. Counter Timing Diagram, Update Event When ARPE=1
  589
- Clock Selection
  590
- Figure 214. Control Circuit in Normal Mode, Internal Clock Divided by 1
  590
- Figure 215. TI2 External Clock Connection Example
  591
- Figure 216. Control Circuit in External Clock Mode 1
  591
- Capture/Compare Channels
  592
- Figure 217. Capture/Compare Channel (Example: Channel 1 Input Stage)
  592
- Figure 218. Capture/Compare Channel 1 Main Circuit
  593
- Figure 219. Output Stage of Capture/Compare Channel (Channel 1)
  593
- Input Capture Mode
  593
- PWM Input Mode (Only for TIM9/12)
  594
- Figure 220. PWM Input Mode Timing
  595
- Forced Output Mode
  595
- Output Compare Mode
  596
- Figure 221. Output Compare Mode, Toggle on OC1
  597
- PWM Mode
  597
- Figure 222. Edge-Aligned PWM Waveforms (ARR=8)
  598
- One-Pulse Mode
  598
- Figure 223. Example of One Pulse Mode
  599
- TIM9/12 External Trigger Synchronization
  600
- Figure 224. Control Circuit in Reset Mode
  601
- Figure 225. Control Circuit in Gated Mode
  602
- Figure 226. Control Circuit in Trigger Mode
  602
- Debug Mode
  603
- TIM9 and TIM12 Registers
  603
- TIM9/12 Control Register 1 (Timx_Cr1)
  603
- Timer Synchronization (TIM9/12)
  603
- TIM9/12 Slave Mode Control Register (Timx_Smcr)
  605
- Table 115. Timx Internal Trigger Connections
  606
- TIM9/12 Interrupt Enable Register (Timx_Dier)
  606
- TIM9/12 Status Register (Timx_Sr)
  607
- TIM9/12 Event Generation Register (Timx_Egr)
  608
- TIM9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)
  609
- TIM9/12 Capture/Compare Enable Register (Timx_Ccer)
  612
- Table 116. Output Control Bit for Standard Ocx Channels
  613
- TIM9/12 Auto-Reload Register (Timx_Arr)
  613
- TIM9/12 Counter (Timx_Cnt)
  613
- TIM9/12 Prescaler (Timx_Psc)
  613
- TIM9/12 Capture/Compare Register 1 (Timx_Ccr1)
  614
- TIM9/12 Capture/Compare Register 2 (Timx_Ccr2)
  614
- Table 117. TIM9/12 Register Map and Reset Values
  615
- TIM9/12 Register Map
  615
- TIM10/11/13/14 Control Register 1 (Timx_Cr1)
  617
- TIM10/11/13/14 Registers
  617
- TIM10/11/13/14 Interrupt Enable Register (Timx_Dier)
  618
- TIM10/11/13/14 Status Register (Timx_Sr)
  618
- TIM10/11/13/14 Event Generation Register (Timx_Egr)
  619
- (Timx_Ccmr1)
  620
- TIM10/11/13/14 Capture/Compare Mode Register 1
  620
- (Timx_Ccer)
  623
- Table 118. Output Control Bit for Standard Ocx Channels
  623
- TIM10/11/13/14 Capture/Compare Enable Register
  623
- TIM10/11/13/14 Auto-Reload Register (Timx_Arr)
  624
- TIM10/11/13/14 Counter (Timx_Cnt)
  624
- TIM10/11/13/14 Prescaler (Timx_Psc)
  624
- TIM10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)
  625
- TIM11 Option Register 1 (TIM11_OR)
  625
- Table 119. TIM10/11/13/14 Register Map and Reset Values
  626
- TIM10/11/13/14 Register Map
  626
- Basic Timers (TIM6&TIM7)
  628
- Figure 227. Basic Timer Block Diagram
  628
- TIM6&TIM7 Introduction
  628
- TIM6&TIM7 Main Features
  628
- TIM6&TIM7 Functional Description
  629
- Time-Base Unit
  629
- Figure 228. Counter Timing Diagram with Prescaler Division Change from 1 to 2
  630
- Figure 229. Counter Timing Diagram with Prescaler Division Change from 1 to 4
  630
- Counting Mode
  631
- Figure 230. Counter Timing Diagram, Internal Clock Divided by 1
  631
- Figure 231. Counter Timing Diagram, Internal Clock Divided by 2
  632
- Figure 232. Counter Timing Diagram, Internal Clock Divided by 4
  632
- Figure 233. Counter Timing Diagram, Internal Clock Divided by N
  632
- Clock Source
  633
- Figure 234. Counter Timing Diagram, Update Event When ARPE = 0
  633
- Figure 235. Counter Timing Diagram, Update Event When ARPE=1
  633
- Debug Mode
  634
- Figure 236. Control Circuit in Normal Mode, Internal Clock Divided by 1
  634
- TIM6&TIM7 Control Register 1 (Timx_Cr1)
  634
- TIM6&TIM7 Registers
  634
- TIM6&TIM7 Control Register 2 (Timx_Cr2)
  636
- TIM6&TIM7 Dma/Interrupt Enable Register (Timx_Dier)
  636
- TIM6&TIM7 Counter (Timx_Cnt)
  637
- TIM6&TIM7 Event Generation Register (Timx_Egr)
  637
- TIM6&TIM7 Status Register (Timx_Sr)
  637
- TIM6&TIM7 Auto-Reload Register (Timx_Arr)
  638
- TIM6&TIM7 Prescaler (Timx_Psc)
  638
- Table 120. TIM6&TIM7 Register Map and Reset Values
  639
- TIM6&TIM7 Register Map
  639
- Hardware Watchdog
  640
- Independent Watchdog (IWDG)
  640
- IWDG Functional Description
  640
- IWDG Introduction
  640
- IWDG Main Features
  640
- Register Access Protection
  640
- Debug Mode
  641
- Figure 237. Independent Watchdog Block Diagram
  641
- Table 121. Min/Max IWDG Timeout Period at 32 Khz (LSI)
  641
- IWDG Registers
  642
- Key Register (IWDG_KR)
  642
- Prescaler Register (IWDG_PR)
  643
- Reload Register (IWDG_RLR)
  644
- Status Register (IWDG_SR)
  644
- IWDG Register Map
  645
- Table 122. IWDG Register Map and Reset Values
  645
- Window Watchdog (WWDG)
  646
- WWDG Functional Description
  646
- WWDG Introduction
  646
- WWDG Main Features
  646
- Figure 238. Watchdog Block Diagram
  647
- Figure 239. Window Watchdog Timing Diagram
  648
- How to Program the Watchdog Timeout
  648
- Debug Mode
  649
- Control Register (WWDG_CR)
  650
- WWDG Registers
  650
- Configuration Register (WWDG_CFR)
  651
- Status Register (WWDG_SR)
  651
- Table 123. WWDG Register Map and Reset Values
  652
- WWDG Register Map
  652
- Introduction
  653
- Real-Time Clock (RTC)
  653
- RTC Main Features
  653
- Clock and Prescalers
  655
- Figure 240. RTC Block Diagram
  655
- Real-Time Clock and Calendar
  655
- RTC Functional Description
  655
- Periodic Auto-Wakeup
  656
- Programmable Alarms
  656
- RTC Initialization and Configuration
  657
- Reading the Calendar
  659
- Resetting the RTC
  660
- RTC Synchronization
  660
- RTC Coarse Digital Calibration
  661
- RTC Reference Clock Detection
  661
- RTC Smooth Digital Calibration
  662
- Timestamp Function
  664
- Tamper Detection
  665
- Alarm Output
  667
- Calibration Clock Output
  667
- RTC and Low Power Modes
  668
- RTC Interrupts
  668
- Table 124. Effect of Low Power Modes on RTC
  668
- Table 125. Interrupt Control Bits
  669
- RTC Registers
  670
- RTC Time Register (RTC_TR)
  670
- RTC Date Register (RTC_DR)
  671
- RTC Control Register (RTC_CR)
  672
- RTC Initialization and Status Register (RTC_ISR)
  674
- RTC Prescaler Register (RTC_PRER)
  676
- RTC Calibration Register (RTC_CALIBR)
  677
- RTC Wakeup Timer Register (RTC_WUTR)
  677
- RTC Alarm a Register (RTC_ALRMAR)
  679
- RTC Alarm B Register (RTC_ALRMBR)
  680
- RTC Sub Second Register (RTC_SSR)
  681
- RTC Write Protection Register (RTC_WPR)
  681
- RTC Shift Control Register (RTC_SHIFTR)
  682
- RTC Time Stamp Date Register (RTC_TSDR)
  683
- RTC Time Stamp Time Register (RTC_TSTR)
  683
- RTC Calibration Register (RTC_CALR)
  684
- RTC Timestamp Sub Second Register (RTC_TSSSR)
  684
- (Rtc_Tafcr)
  685
- RTC Tamper and Alternate Function Configuration Register
  685
- RTC Alarm a Sub Second Register (RTC_ALRMASSR)
  687
- RTC Alarm B Sub Second Register (RTC_ALRMBSSR)
  688
- RTC Backup Registers (Rtc_Bkpxr)
  689
- RTC Register Map
  690
- Table 126. RTC Register Map and Reset Values
  690
- Fast-Mode Plus Inter-Integrated Circuit (FMPI2C) Interface
  692
- FMPI2C Main Features
  692
- Introduction
  692
- FMPI2C Functional Description
  693
- FMPI2C Implementation
  693
- Table 127. Stm32F446Xx FMPI2C Implementation
  693
- Figure 241. FMPI2C Block Diagram
  694
- FMPI2C Block Diagram
  694
- FMPI2C Clock Requirements
  695
- Mode Selection
  695
- Figure 242. I2C Bus Protocol
  696
- FMPI2C Initialization
  696
- Figure 243. Setup and Hold Timings
  697
- Table 128. I2C-SMBUS Specification Data Setup and Hold Times
  698
- Figure 244. FMPI2C Initialization Flowchart
  700
- Software Reset
  700
- Data Transfer
  701
- Figure 245. Data Reception
  701
- Figure 246. Data Transmission
  702
- FMPI2C Slave Mode
  703
- Table 129. FMPI2C Configuration
  703
- Figure 247. Slave Initialization Flowchart
  705
- Figure 248. Transfer Sequence Flowchart for FMPI2C Slave Transmitter, NOSTRETCH=0
  707
- Figure 249. Transfer Sequence Flowchart for FMPI2C Slave Transmitter, NOSTRETCH=1
  708
- Figure 250. Transfer Bus Diagrams for FMPI2C Slave Transmitter
  709
- Figure 251. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=0
  710
- Figure 252. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=1
  711
- Figure 253. Transfer Bus Diagrams for FMPI2C Slave Receiver
  711
- FMPI2C Master Mode
  712
- Figure 254. Master Clock Generation
  713
- Table 130. I2C-SMBUS Specification Clock Timings
  714
- Figure 255. Master Initialization Flowchart
  715
- Figure 256. 10-Bit Address Read Access with HEAD10R=0
  715
- Figure 257. 10-Bit Address Read Access with HEAD10R=1
  716
- Figure 258. Transfer Sequence Flowchart for FMPI2C Master Transmitter for N≤255 Bytes
  717
- Figure 259. Transfer Sequence Flowchart for FMPI2C Master Transmitter for N>255 Bytes
  718
- Figure 260. Transfer Bus Diagrams for FMPI2C Master Transmitter
  719
- Figure 261. Transfer Sequence Flowchart for FMPI2C Master Receiver for N≤255 Bytes
  721
- Figure 262. Transfer Sequence Flowchart for FMPI2C Master Receiver for N >255 Bytes
  722
- Figure 263. Transfer Bus Diagrams for FMPI2C Master Receiver
  723
- FMPI2C_TIMINGR Register Configuration Examples
  724
- Table 131. Examples of Timing Settings for Fi2Cclk = 8 Mhz
  724
- Table 132. Examples of Timings Settings for Fi2Cclk = 16 Mhz
  724
- Smbus Specific Features
  725
- Figure 264. Timeout Intervals for T
  727
- Table 133. Smbus Timeout Specifications
  727
- Smbus Initialization
  728
- Table 134. SMBUS with PEC Configuration
  729
- Table 135. Examples of TIMEOUTA Settings for Various FMPI2CCLK Frequencies
  729
- Smbus Slave Mode
  730
- Smbus: FMPI2C_TIMEOUTR Register Configuration Examples
  730
- Table 136. Examples of TIMEOUTB Settings for Various FMPI2CCLK Frequencies
  730
- Table 137. Examples of TIMEOUTA Settings for Various FMPI2CCLK Frequencies (Max T IDLE = 50 Μs)
  730
- Figure 265. Transfer Sequence Flowchart for Smbus Slave Transmitter N Bytes + PEC
  731
- Figure 266. Transfer Bus Diagrams for Smbus Slave Transmitter (SBC=1)
  732
- Figure 267. Transfer Sequence Flowchart for Smbus Slave Receiver N Bytes + PEC
  733
- Figure 268. Bus Transfer Diagrams for Smbus Slave Receiver (SBC=1)
  734
- Figure 269. Bus Transfer Diagrams for Smbus Master Transmitter
  735
- Error Conditions
  737
- Figure 270. Bus Transfer Diagrams for Smbus Master Receiver
  737
- DMA Requests
  739
- Debug Mode
  740
- FMPI2C Low-Power Modes
  740
- Table 138. Low-Power Modes
  740
- Figure 271. FMPI2C Interrupt Mapping Diagram
  741
- FMPI2C Interrupts
  741
- Table 139. FMPI2C Interrupt Requests
  741
- Control Register 1 (FMPI2C_CR1)
  742
- FMPI2C Registers
  742
- Control Register 2 (FMPI2C_CR2)
  745
- Own Address 1 Register (FMPI2C_OAR1)
  748
- Own Address 2 Register (FMPI2C_OAR2)
  749
- Timing Register (FMPI2C_TIMINGR)
  750
- Timeout Register (FMPI2C_TIMEOUTR)
  751
- Interrupt and Status Register (FMPI2C_ISR)
  752
- Interrupt Clear Register (FMPI2C_ICR)
  754
- PEC Register (FMPI2C_PECR)
  755
- Receive Data Register (FMPI2C_RXDR)
  756
- Transmit Data Register (FMPI2C_TXDR)
  756
- FMPI2C Register Map
  757
- Table 140. FMPI2C Register Map and Reset Values
  757
- I 2 C Introduction
  759
- Inter-Integrated Circuit (I 2 C) Interface
  759
- I 2 C Main Features
  760
- C Functional Description
  761
- Figure 272. I2C Bus Protocol
  761
- Mode Selection
  761
- Figure 273. I2C Block Diagram
  762
- I2C Slave Mode
  762
- Figure 274. Transfer Sequence Diagram for Slave Transmitter
  764
- Figure 275. Transfer Sequence Diagram for Slave Receiver
  765
- I2C Master Mode
  765
- Figure 276. Transfer Sequence Diagram for Master Transmitter
  768
- Figure 277. Transfer Sequence Diagram for Master Receiver
  770
- Error Conditions
  771
- Programmable Noise Filter
  772
- Table 141. Maximum DNF[3:0] Value to be Compliant with Thd:dat(Max)
  772
- SDA/SCL Line Control
  773
- Smbus
  773
- Table 142. Smbus Vs. I2C
  774
- DMA Requests
  776
- Packet Error Checking
  777
- I 2 C Interrupts
  778
- Table 143. I2C Interrupt Requests
  778
- Figure 278. I2C Interrupt Mapping Diagram
  779
- C Registers
  780
- I 2 C Control Register 1 (I2C_CR1)
  780
- I 2 C Debug Mode
  780
- I 2 C Control Register 2 (I2C_CR2)
  782
- I 2 C Own Address Register 1 (I2C_OAR1)
  784
- I 2 C Own Address Register 2 (I2C_OAR2)
  784
- C Data Register (I2C_DR)
  785
- C Status Register 1 (I2C_SR1)
  785
- I 2 C Status Register 2 (I2C_SR2)
  789
- I 2 C Clock Control Register (I2C_CCR)
  790
- C TRISE Register (I2C_TRISE)
  791
- I 2 C FLTR Register (I2C_FLTR)
  792
- I2C Register Map
  793
- Table 144. I2C Register Map and Reset Values
  793
- Transmitter (USART)
  794
- Universal Synchronous Asynchronous Receiver
  794
- USART Introduction
  794
- USART Main Features
  795
- Table 145. USART Features
  796
- USART Functional Description
  796
- USART Implementation
  796
- Figure 279. USART Block Diagram
  798
- Figure 280. Word Length Programming
  799
- USART Character Description
  799
- Transmitter
  800
- Figure 281. Configurable Stop Bits
  801
- Figure 282. TC/TXE Behavior When Transmitting
  802
- Figure 283. Start Bit Detection When Oversampling by 16 or 8
  803
- Receiver
  803
- Figure 284. Data Sampling When Oversampling by 16
  806
- Figure 285. Data Sampling When Oversampling by 8
  807
- Table 146. Noise Detection from Sampled Data
  807
- Fractional Baud Rate Generation
  808
- Table 147. Error Calculation for Programmed Baud Rates at F
  810
- Table 157. USART Receiver Tolerance When DIV Fraction Is 0
  817
- USART Receiver Tolerance to Clock Deviation
  817
- Multiprocessor Communication
  818
- Table 158. USART Receiver Tolerance When Div_Fraction Is Different from 0
  818
- Figure 286. Mute Mode Using Idle Line Detection
  819
- Figure 287. Mute Mode Using Address Mark Detection
  819
- Parity Control
  820
- Table 159. Frame Formats
  820
- LIN (Local Interconnection Network) Mode
  821
- Figure 288. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)
  822
- Figure 289. Break Detection in LIN Mode Vs. Framing Error Detection
  823
- USART Synchronous Mode
  823
- Figure 290. USART Example of Synchronous Transmission
  824
- Figure 291. USART Data Clock Timing Diagram (M=0)
  824
- Figure 292. USART Data Clock Timing Diagram (M=1)
  825
- Figure 293. RX Data Setup/Hold Time
  825
- Single-Wire Half-Duplex Communication
  825
- Figure 294. ISO 7816-3 Asynchronous Protocol
  826
- Smartcard
  826
- Figure 295. Parity Error Detection Using the 1.5 Stop Bits
  827
- Irda SIR ENDEC Block
  828
- Figure 296. Irda SIR ENDEC- Block Diagram
  829
- Figure 297. Irda Data Modulation (3/16) -Normal Mode
  829
- Continuous Communication Using DMA
  830
- Figure 298. Transmission Using DMA
  831
- Figure 299. Reception Using DMA
  832
- Figure 300. Hardware Flow Control between 2 Usarts
  832
- Hardware Flow Control
  832
- Figure 301. RTS Flow Control
  833
- Figure 302. CTS Flow Control
  833
- Table 160. USART Interrupt Requests
  834
- USART Interrupts
  834
- Figure 303. USART Interrupt Mapping Diagram
  835
- Status Register (USART_SR)
  835
- USART Registers
  835
- Baud Rate Register (USART_BRR)
  838
- Data Register (USART_DR)
  838
- Control Register 1 (USART_CR1)
  839
- Control Register 2 (USART_CR2)
  841
- Control Register 3 (USART_CR3)
  842
- Guard Time and Prescaler Register (USART_GTPR)
  844
- Table 161. USART Register Map and Reset Values
  845
- USART Register Map
  845
- Introduction
  846
- Serial Peripheral Interface/ Inter-IC Sound (SPI/I2S)
  846
- SPI Main Features
  846
- I2S Features
  847
- SPI Extended Features
  847
- SPI/I2S Implementation
  847
- Table 162. Stm32F446Xx SPI Implementation
  847
- Figure 304. SPI Block Diagram
  848
- General Description
  848
- SPI Functional Description
  848
- Communications between One Master and One Slave
  849
- Figure 305. Full-Duplex Single Master/ Single Slave Application
  849
- Figure 306. Half-Duplex Single Master/ Single Slave Application
  850
- Figure 307. Simplex Single Master/Single Slave Application
  851
- Figure 308. Master and Three Independent Slaves
  852
- Standard Multi-Slave Communication
  852
- Figure 309. Multi-Master Application
  853
- Multi-Master Communication
  853
- Slave Select (NSS) Pin Management
  853
- Figure 310. Hardware/Software Slave Select Management
  854
- Communication Formats
  855
- Figure 311. Data Clock Timing Diagram
  856
- Procedure for Enabling SPI
  857
- SPI Configuration
  857
- Data Transmission and Reception Procedures
  858
- Figure 312. TXE/RXNE/BSY Behavior in Master / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the Case of Continuous Transfers
  859
- Figure 313. TXE/RXNE/BSY Behavior in Slave / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the Case of Continuous Transfers
  860
- Procedure for Disabling the SPI
  860
- Communication Using DMA (Direct Memory Addressing)
  861
- Figure 314. Transmission Using DMA
  862
- Figure 315. Reception Using DMA
  863
- SPI Status Flags
  863
- SPI Error Flags
  864
- SPI Special Features
  865
- TI Mode
  865
- CRC Calculation
  866
- Figure 316. TI Mode Transfer
  866
- SPI Interrupts
  868
- Table 163. SPI Interrupt Requests
  868
- Figure 317. I 2 S Block Diagram
  869
- I 2 S Functional Description
  869
- I 2 S General Description
  869
- I2S Full-Duplex
  870
- Figure 318. Full-Duplex Communication
  871
- Supported Audio Protocols
  871
- Figure 319. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy, CPOL = 0)
  872
- Figure 320. I 2 S Philips Standard Waveforms (24-Bit Frame with CPOL = 0)
  872
- Figure 321. Transmitting 0X8Eaa33
  873
- Figure 322. Receiving 0X8Eaa33
  873
- Figure 323. I
  873
- Figure 324. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame
  874
- Figure 325. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length with CPOL = 0
  874
- Figure 326. MSB Justified 24-Bit Frame Length with CPOL = 0
  874
- Figure 327. MSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
  875
- Figure 328. LSB Justified 16-Bit or 32-Bit Full-Accuracy with CPOL = 0
  875
- Figure 329. LSB Justified 24-Bit Frame Length with CPOL = 0
  875
- Figure 330. Operations Required to Transmit 0X3478Ae
  876
- Figure 331. Operations Required to Receive 0X3478Ae
  876
- Figure 332. LSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
  876
- Figure 333. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame
  877
- Figure 334. PCM Standard Waveforms (16-Bit)
  877
- Figure 335. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)
  877
- Clock Generator
  878
- Figure 336. Audio Sampling Frequency Definition
  878
- Figure 337. I
  878
- Table 164. Audio-Frequency Precision Using Standard 8 Mhz HSE
  879
- I 2 S Master Mode
  880
- I 2 S Slave Mode
  882
- I 2 S Status Flags
  883
- I 2 S Error Flags
  884
- DMA Features
  885
- I 2 S Interrupts
  885
- Table 165. I
  885
- SPI and I 2 S Registers
  886
- SPI Control Register 1 (SPI_CR1) (Not Used in I 2 S Mode)
  886
- SPI Control Register 2 (SPI_CR2)
  888
- SPI Status Register (SPI_SR)
  889
- Mode
  891
- SPI CRC Polynomial Register (SPI_CRCPR) (Not Used in I
  891
- SPI Data Register (SPI_DR)
  891
- SPI RX CRC Register (SPI_RXCRCR) (Not Used in I 2 S Mode)
  892
- SPI TX CRC Register (SPI_TXCRCR) (Not Used in I 2 S Mode)
  892
- SPI_I 2 S Configuration Register (SPI_I2SCFGR)
  893
- SPI_I 2 S Prescaler Register (SPI_I2SPR)
  894
- SPI Register Map
  896
- Table 166. SPI Register Map and Reset Values
  896
- SPDIF Receiver Interface (SPDIFRX)
  897
- SPDIFRX Functional Description
  897
- SPDIFRX Interface Introduction
  897
- SPDIFRX Main Features
  897
- Figure 338. SPDIFRX Block Diagram
  898
- Figure 339. S/PDIF Sub-Frame Format
  898
- S/PDIF Protocol (IEC-60958)
  898
- Figure 340. S/PDIF Block Format
  899
- Figure 341. S/PDIF Preambles
  899
- Figure 342. Channel Coding Example
  900
- SPDIFRX Decoder (SPDIFRX_DC)
  900
- Figure 343. SPDIFRX Decoder
  901
- Figure 344. Noise Filtering and Edge Detection
  901
- Figure 345. Thresholds
  903
- Table 167. Transition Sequence for Preamble
  903
- SPDIFRX Synchronization
  904
- SPDIFRX Tolerance to Clock Deviation
  904
- Figure 346. Synchronization Flowchart
  905
- Figure 347. Synchronization Process Scheduling
  906
- SPDIFRX Handling
  906
- Figure 348. SPDIFRX States
  907
- Data Reception Management
  908
- Figure 349. SPDIFRX_DR Register Format
  909
- Dedicated Control Flow
  910
- Figure 350. Channel/User Data Format
  910
- Reception Errors
  910
- Figure 351. S/PDIF Overrun Error When RXSTEO = 0
  912
- Clocking Strategy
  913
- DMA Interface
  913
- Figure 352. S/PDIF Overrun Error When RXSTEO = 1
  913
- Table 168. Minimum SPDIFRX_CLK Frequency Versus Audio Sampling Rate
  913
- Figure 353. SPDIFRX Interface Interrupt Mapping Diagram
  914
- Interrupt Generation
  914
- Programming Procedures
  915
- Register Protection
  915
- Table 169. Bit Field Property Versus SPDIFRX State
  915
- Initialization Phase
  916
- Handling of Interrupts Coming from DMA
  917
- Handling of Interrupts Coming from SPDIFRX
  917
- Control Register (SPDIFRX_CR)
  918
- SPDIFRX Interface Registers
  918
- Interrupt Mask Register (SPDIFRX_IMR)
  920
- Status Register (SPDIFRX_SR)
  921
- Interrupt Flag Clear Register (SPDIFRX
  923
- Data Input Register (SPDIFRX_DR)
  924
- Data Input Register (SPDIFRX_FMT1_DR)
  925
- Data Input Register (SPDIFRX_FMT2_DR)
  926
- Channel Status Register (SPDIFRX_CSR)
  927
- Debug Information Register (SPDIFRX_DIR)
  927
- SPDIFRX Interface Register Map
  929
- Table 170. SPDIFRX Interface Register Map and Reset Values
  929
- Introduction
  930
- Serial Audio Interface (SAI)
  930
- SAI Main Features
  931
- Figure 354. SAI Functional Block Diagram
  932
- SAI Block Diagram
  932
- SAI Functional Description
  932
- Main SAI Modes
  933
- SAI Pins and Internal Signals
  933
- Table 171. SAI Internal Input/Output Signals
  933
- Table 172. SAI Input/Output Pins
  933
- SAI Synchronization Mode
  934
- Audio Data Size
  935
- Table 173. External Synchronization Selection
  935
- Figure 355. Audio Frame
  936
- Frame Synchronization
  936
- Figure 356. FS Role Is Start of Frame + Channel Side Identification (FSDEF = TRIS = 1)
  938
- Figure 357. FS Role Is Start of Frame (FSDEF = 0)
  939
- Slot Configuration
  939
- Figure 358. Slot Size Configuration with FBOFF = 0 in Sai_Xslotr
  940
- Figure 359. First Bit Offset
  940
- Figure 360. Audio Block Clock Generator Overview
  941
- SAI Clock Generator
  941
- Table 174. Example of Possible Audio Frequency Sampling Range
  942
- Internal Fifos
  943
- AC'97 Link Controller
  945
- Figure 361. AC'97 Audio Frame
  945
- Figure 362. Example of Typical AC'97 Configuration on Devices Featuring at Least
  946
- Figure 363. SPDIF Format
  947
- SPDIF Output
  947
- Figure 364. Sai_Xdr Register Ordering
  948
- Table 175. SOPD Pattern
  948
- Table 176. Parity Bit Calculation
  948
- Table 177. Audio Sampling Frequency Versus Symbol Rates
  949
- Specific Features
  950
- Figure 365. Data Companding Hardware in an Audio Block in the SAI
  951
- Figure 366. Tristate Strategy on SD Output Line on an Inactive Slot
  953
- Error Flags
  954
- Figure 367. Tristate on Output Data Line in a Protocol Like I2S
  954
- Figure 368. Overrun Detection Error
  955
- Figure 369. FIFO Underrun Event
  955
- Disabling the SAI
  957
- SAI DMA Interface
  957
- SAI Interrupts
  958
- Table 178. SAI Interrupt Sources
  958
- Configuration Register 1 (SAI_ACR1 / SAI_BCR1)
  959
- Global Configuration Register (SAI_GCR)
  959
- SAI Registers
  959
- Configuration Register 2 (SAI_ACR2 / SAI_BCR2)
  962
- Frame Configuration Register (SAI_AFRCR / SAI_BFRCR)
  964
- Slot Register (SAI_ASLOTR / SAI_BSLOTR)
  966
- Interrupt Mask Register 2 (SAI_AIM / SAI_BIM)
  967
- Status Register (SAI_ASR / SAI_BSR)
  968
- Clear Flag Register (SAI_ACLRFR / SAI_BCLRFR)
  970
- Data Register (SAI_ADR / SAI_BDR)
  971
- SAI Register Map
  973
- Table 179. SAI Register Map and Reset Values
  973
- SDIO Bus Topology
  974
- SDIO Main Features
  974
- Secure Digital Input/Output Interface (SDIO)
  974
- Figure 370. "No Response" and "No Data" Operations
  975
- Figure 371. (Multiple) Block Read Operation
  975
- Figure 372. (Multiple) Block Write Operation
  975
- Figure 373. Sequential Read Operation
  976
- Figure 374. Sequential Write Operation
  976
- Figure 375. SDIO Block Diagram
  976
- SDIO Functional Description
  976
- Table 180. SDIO I/O Definitions
  977
- Figure 376. SDIO Adapter
  978
- SDIO Adapter
  978
- Figure 377. Control Unit
  979
- Figure 378. SDIO_CK Clock Dephasing (BYPASS = 0)
  979
- Figure 379. SDIO Adapter Command Path
  980
- Figure 380. Command Path State Machine (SDIO)
  981
- Figure 381. SDIO Command Transfer
  982
- Table 181. Command Format
  982
- Table 182. Short Response Format
  983
- Table 183. Long Response Format
  983
- Table 184. Command Path Status Flags
  983
- Figure 382. Data Path
  984
- Figure 383. Data Path State Machine (DPSM)
  985
- Table 185. Data Token Format
  986
- Table 186. DPSM Flags
  987
- Table 187. Transmit FIFO Status Flags
  988
- Table 188. Receive FIFO Status Flags
  988
- SDIO APB2 Interface
  989
- Card Functional Description
  990
- Card Identification Mode
  990
- Card Identification Process
  991
- Card Reset
  991
- Operating Voltage Range Validation
  991
- Block Write
  992
- Block Read
  993
- Stream Access, Stream Write and Stream Read (Multimediacard Only)
  993
- Erase: Group Erase and Sector Erase
  995
- Protection Management
  995
- Wide Bus Selection or Deselection
  995
- Card Status Register
  999
- Table 189. Card Status
  999
- SD Status Register
  1002
- Table 190. SD Status
  1002
- Table 191. Speed Class Code Field
  1003
- Table 192. Performance Move Field
  1004
- Table 193. AU_SIZE Field
  1004
- Table 194. Maximum AU Size
  1004
- Table 195. Erase Size Field
  1005
- Table 196. Erase Timeout Field
  1005
- Table 197. Erase Offset Field
  1005
- SD I/O Mode
  1006
- Commands and Responses
  1007
- Table 198. Block-Oriented Write Commands
  1008
- Table 199. Block-Oriented Write Protection Commands
  1009
- Table 200. Erase Commands
  1009
- Table 201. I/O Mode Commands
  1009
- Response Formats
  1010
- Table 202. Lock Card
  1010
- Table 203. Application-Specific Commands
  1010
- R1 (Normal Response Command)
  1011
- R1B
  1011
- R2 (CID, CSD Register)
  1011
- Table 204. R1 Response
  1011
- Table 205. R2 Response
  1011
- R3 (OCR Register)
  1012
- R4 (Fast I/O)
  1012
- R4B
  1012
- Table 206. R3 Response
  1012
- Table 207. R4 Response
  1012
- Table 208. R4B Response
  1012
- R5 (Interrupt Request)
  1013
- Table 209. R5 Response
  1013
- SDIO I/O Card-Specific Operations
  1014
- SDIO I/O Read Wait Operation by SDIO_D2 Signalling
  1014
- Table 210. R6 Response
  1014
- HW Flow Control
  1015
- SDIO Interrupts
  1015
- SDIO Read Wait Operation by Stopping SDIO_CK
  1015
- SDIO Suspend/Resume Operation
  1015
- SDIO Clock Control Register (SDIO_CLKCR)
  1016
- SDIO Power Control Register (SDIO_POWER)
  1016
- SDIO Registers
  1016
- SDIO Argument Register (SDIO_ARG)
  1018
- SDIO Command Register (SDIO_CMD)
  1018
- SDIO Command Response Register (SDIO_RESPCMD)
  1019
- SDIO Response 1
  1019
- SDIO Data Timer Register (SDIO_DTIMER)
  1020
- Table 211. Response Type and Sdio_Respx Registers
  1020
- SDIO Data Control Register (SDIO_DCTRL)
  1021
- SDIO Data Length Register (SDIO_DLEN)
  1021
- SDIO Data Counter Register (SDIO_DCOUNT)
  1023
- SDIO Status Register (SDIO_STA)
  1023
- SDIO Interrupt Clear Register (SDIO_ICR)
  1024
- SDIO Mask Register (SDIO_MASK)
  1026
- SDIO FIFO Counter Register (SDIO_FIFOCNT)
  1028
- SDIO Data FIFO Register (SDIO_FIFO)
  1029
- SDIO Register Map
  1030
- Table 212. SDIO Register Map
  1030
- Bxcan Main Features
  1032
- Controller Area Network (Bxcan)
  1032
- Introduction
  1032
- Bxcan General Description
  1033
- CAN 2.0B Active Core
  1033
- Control, Status and Configuration Registers
  1033
- Figure 384. CAN Network Topology
  1033
- Tx Mailboxes
  1033
- Acceptance Filters
  1034
- Figure 385. Dual-CAN Block Diagram
  1034
- Bxcan Operating Modes
  1035
- Initialization Mode
  1035
- Normal Mode
  1035
- Figure 386. Bxcan Operating Modes
  1036
- Sleep Mode (Low-Power)
  1036
- Figure 387. Bxcan in Silent Mode
  1037
- Figure 388. Bxcan in Loop Back Mode
  1037
- Loop Back Mode
  1037
- Silent Mode
  1037
- Test Mode
  1037
- Behavior in Debug Mode
  1038
- Bxcan Functional Description
  1038
- Figure 389. Bxcan in Combined Mode
  1038
- Loop Back Combined with Silent Mode
  1038
- Transmission Handling
  1038
- Figure 390. Transmit Mailbox States
  1040
- Reception Handling
  1040
- Time Triggered Communication Mode
  1040
- Figure 391. Receive FIFO States
  1041
- Identifier Filtering
  1042
- Figure 392. Filter Bank Scale Configuration - Register Organization
  1044
- Figure 393. Example of Filter Numbering
  1045
- Figure 394. Filtering Mechanism - Example
  1046
- Message Storage
  1046
- Figure 395. CAN Error State Diagram
  1047
- Table 213. Transmit Mailbox Mapping
  1047
- Table 214. Receive Mailbox Mapping
  1047
- Bit Timing
  1048
- Error Management
  1048
- Figure 396. Bit Timing
  1049
- Figure 397. CAN Frames
  1050
- Bxcan Interrupts
  1051
- Figure 398. Event Flags and Interrupt Generation
  1051
- CAN Control and Status Registers
  1052
- CAN Registers
  1052
- Register Access Protection
  1052
- CAN Mailbox Registers
  1062
- Figure 399. CAN Mailbox Registers
  1063
- CAN Filter Registers
  1069
- Bxcan Register Map
  1073
- Table 215. Bxcan Register Map and Reset Values
  1073
- Introduction
  1077
- USB On-The-Go Full-Speed/High-Speed (OTG_FS/OTG_HS)
  1077
- OTG Main Features
  1078
- Table 216. OTG_HS Speeds Supported
  1078
- Table 217. OTG_FS Speeds Supported
  1078
- General Features
  1079
- Host-Mode Features
  1080
- Peripheral-Mode Features
  1080
- OTG Implementation
  1081
- Table 218. OTG Implementation for Stm32F446Xx
  1081
- Figure 400. OTG Full-Speed Block Diagram
  1082
- OTG Block Diagram
  1082
- OTG Functional Description
  1082
- Figure 401. OTG High-Speed Block Diagram
  1083
- Table 219. OTG_FS Input/Output Pins
  1083
- Table 220. OTG_HS Input/Output Pins
  1083
- USB OTG Pin and Internal Signals
  1083
- Full-Speed OTG PHY
  1084
- OTG Core
  1084
- Table 221. OTG_FS/OTG_HS Input/Output Signals
  1084
- Embedded Full Speed OTG PHY
  1085
- Figure 402. OTG_FS A-B Device Connection
  1086
- High-Speed OTG PHY
  1086
- ID Line Detection
  1086
- OTG Dual Role Device (DRD)
  1086
- HNP Dual Role Device
  1087
- SRP Dual Role Device
  1087
- USB Peripheral
  1087
- Figure 403. USB_FS Peripheral-Only Connection
  1088
- Peripheral States
  1088
- SRP-Capable Peripheral
  1088
- Peripheral Endpoints
  1089
- USB Host
  1091
- Figure 404. USB_FS Host-Only Connection
  1092
- SRP-Capable Host
  1092
- USB Host States
  1092
- Host Channels
  1094
- Host Scheduler
  1095
- Figure 405. SOF Connectivity (SOF Trigger Output to TIM and ITR1 Connection)
  1096
- Host Sofs
  1096
- Peripheral Sofs
  1096
- SOF Trigger
  1096
- OTG Low-Power Modes
  1097
- Table 222. Compatibility of STM32 Low Power Modes with the OTG
  1097
- Dynamic Update of the OTG_HFIR Register
  1098
- Figure 406. Updating OTG_HFIR Dynamically (RLDCTRL = 0)
  1098
- USB Data Fifos
  1098
- Figure 407. Device-Mode FIFO Address Mapping and AHB FIFO Access Mapping
  1099
- Peripheral FIFO Architecture
  1099
- Figure 408. Host-Mode FIFO Address Mapping and AHB FIFO Access Mapping
  1100
- Host FIFO Architecture
  1100
- FIFO RAM Allocation
  1101
- OTG_FS System Performance
  1103
- OTG_FS/OTG_HS Interrupts
  1103
- Figure 409. Interrupt Hierarchy
  1104
- CSR Memory Map
  1105
- OTG_FS/OTG_HS Control and Status Registers
  1105
- Table 223. Core Global Control and Status Registers (Csrs)
  1105
- Table 224. Host-Mode Control and Status Registers (Csrs)
  1106
- Table 225. Device-Mode Control and Status Registers
  1108
- Table 226. Data FIFO (DFIFO) Access Register Map
  1110
- OTG Control and Status Register (OTG_GOTGCTL)
  1111
- OTG_FS/OTG_HS Registers
  1111
- Table 227. Power and Clock Gating Control and Status Registers
  1111
- OTG Interrupt Register (OTG_GOTGINT)
  1114
- OTG AHB Configuration Register (OTG_GAHBCFG)
  1116
- OTG USB Configuration Register (OTG_GUSBCFG)
  1118
- OTG Reset Register (OTG_GRSTCTL)
  1121
- Table 228. TRDT Values (FS)
  1121
- Table 229. TRDT Values (HS)
  1121
- OTG Core Interrupt Register (OTG_GINTSTS)
  1124
- OTG Interrupt Mask Register (OTG_GINTMSK)
  1129
- OTG Receive Status Debug Read/Otg Status Read and Pop Registers (OTG_GRXSTSR/OTG_GRXSTSP)
  1132
- (Otg_Dieptxf0)
  1135
- OTG Host Non-Periodic Transmit FIFO Size Register (Otg_Hnptxfsiz)/Endpoint 0 Transmit FIFO Size
  1135
- OTG Receive FIFO Size Register (OTG_GRXFSIZ)
  1135
- (Otg_Hnptxsts)
  1136
- OTG General Core Configuration Register (OTG_GCCFG)
  1137
- OTG Core ID Register (OTG_CID)
  1138
- OTG Core LPM Configuration Register (OTG_GLPMCFG)
  1138
- (Otg_Hptxfsiz)
  1143
- 31.15.15 OTG Host Periodic Transmit FIFO Size Register
  1143
- FIFO Number)
  1143
- OTG Device in Endpoint Transmit FIFO Size Register (Otg_Dieptxfx)
  1143
- 31.15.17 Host-Mode Registers
  1144
- OTG Host Configuration Register (OTG_HCFG)
  1144
- OTG Host Frame Interval Register (OTG_HFIR)
  1145
- (Otg_Hfnum)
  1146
- (Otg_Hptxsts)
  1146
- 31.15.20 OTG Host Frame Number/Frame Time Remaining Register
  1146
- 31.15.21 Otg_Host Periodic Transmit Fifo/Queue Status Register
  1146
- OTG Host All Channels Interrupt Register (OTG_HAINT)
  1147
- (Otg_Haintmsk)
  1148
- 31.15.23 OTG Host All Channels Interrupt Mask Register
  1148
- OTG Host Port Control and Status Register (OTG_HPRT)
  1149
- (X = 0
  1151
- OTG Host Channel X Characteristics Register (Otg_Hccharx)
  1151
- (X = 0
  1152
- OTG Host Channel X Split Control Register (Otg_Hcspltx)
  1152
- (X = 0
  1153
- OTG Host Channel X Interrupt Register (Otg_Hcintx)
  1153
- (X = 0
  1155
- OTG Host Channel X Interrupt Mask Register (Otg_Hcintmskx)
  1155
- (X = 0
  1156
- OTG Host Channel X Transfer Size Register (Otg_Hctsizx)
  1156
- (X = 0
  1157
- 31.15.31 Device-Mode Registers
  1157
- OTG Host Channel X DMA Address Register (Otg_Hcdmax)
  1157
- OTG Device Configuration Register (OTG_DCFG)
  1158
- OTG Device Control Register (OTG_DCTL)
  1160
- Table 230. Minimum Duration for Soft Disconnect
  1161
- OTG Device Status Register (OTG_DSTS)
  1162
- (Otg_Diepmsk)
  1163
- 31.15.35 OTG Device in Endpoint Common Interrupt Mask Register
  1163
- (Otg_Doepmsk)
  1164
- 31.15.36 OTG Device out Endpoint Common Interrupt Mask Register
  1164
- (Otg_Daintmsk)
  1166
- 31.15.38 OTG All Endpoints Interrupt Mask Register
  1166
- OTG Device All Endpoints Interrupt Register (OTG_DAINT)
  1166
- (Otg_Dvbusdis)
  1167
- (Otg_Dvbuspulse)
  1167
- Bus
  1167
- BUS Discharge Time Register
  1167
- OTG Device
  1167
- OTG Device Threshold Control Register (OTG_DTHRCTL)
  1168
- (Otg_Diepempmsk)
  1169
- 31.15.42 OTG Device in Endpoint FIFO Empty Interrupt Mask Register
  1169
- (Otg_Deachintmsk)
  1170
- 31.15.44 OTG Device each Endpoint Interrupt Mask Register
  1170
- OTG Device each Endpoint Interrupt Register (OTG_DEACHINT)
  1170
- OTG Device each in Endpoint-1 Interrupt Mask Register (OTG_HS_DIEPEACHMSK1)
  1171
- OTG Device each out Endpoint-1 Interrupt Mask Register (OTG_HS_DOEPEACHMSK1)
  1172
- (Otg_Diepctl0)
  1173
- 31.15.47 OTG Device Control in Endpoint 0 Control Register
  1173
- (X = 1
  1175
- OTG Device in Endpoint X Control Register (Otg_Diepctlx)
  1175
- (X = 0
  1177
- OTG Device in Endpoint X Interrupt Register (Otg_Diepintx)
  1177
- (Otg_Dieptsiz0)
  1179
- 31.15.50 OTG Device in Endpoint 0 Transfer Size Register
  1179
- (X = 0
  1180
- Endpoint Number)
  1180
- OTG Device in Endpoint Transmit FIFO Status Register (Otg_Dtxfstsx)
  1180
- OTG Device in Endpoint X DMA Address Register (Otg_Diepdmax)
  1180
- (X = 1
  1181
- OTG Device in Endpoint X Transfer Size Register (Otg_Dieptsizx)
  1181
- (Otg_Doepctl0)
  1182
- 31.15.54 OTG Device Control out Endpoint 0 Control Register
  1182
- (X = 0
  1183
- OTG Device out Endpoint X Interrupt Register (Otg_Doepintx)
  1183
- (Otg_Doeptsiz0)
  1185
- 31.15.56 OTG Device out Endpoint 0 Transfer Size Register
  1185
- (X = 0
  1186
- OTG Device out Endpoint X DMA Address Register (Otg_Doepdmax)
  1186
- (X = 1
  1187
- OTG Device out Endpoint X Control Register (Otg_Doepctlx)
  1187
- OTG Device out Endpoint X Transfer Size Register (Otg_Doeptsizx) (X = 1
  1189
- OTG Power and Clock Gating Control Register (OTG_PCGCCTL)
  1190
- 31.15.61 OTG_FS/OTG_HS Register Map
  1191
- Table 231. OTG_FS/OTG_HS Register Map and Reset Values
  1191
- Core Initialization
  1203
- Host Initialization
  1203
- OTG_FS/OTG_HS Programming Model
  1203
- Device Initialization
  1204
- DMA Mode
  1205
- Host Programming Model
  1205
- Figure 410. Transmit FIFO Write Task
  1207
- Figure 411. Receive FIFO Read Task
  1208
- Figure 412. Normal Bulk/Control OUT/SETUP
  1210
- Figure 413. Bulk/Control in Transactions
  1214
- Figure 414. Normal Interrupt out
  1217
- Figure 415. Normal Interrupt in
  1222
- Figure 416. Isochronous out Transactions
  1224
- Figure 417. Isochronous in Transactions
  1227
- Figure 418. Normal Bulk/Control OUT/SETUP Transactions - DMA
  1229
- Figure 419. Normal Bulk/Control in Transaction - DMA
  1231
- Figure 420. Normal Interrupt out Transactions - DMA Mode
  1232
- Figure 421. Normal Interrupt in Transactions - DMA Mode
  1233
- Figure 422. Normal Isochronous out Transaction - DMA Mode
  1234
- Figure 423. Normal Isochronous in Transactions - DMA Mode
  1235
- Device Programming Model
  1238
- Figure 424. Receive FIFO Packet Read
  1241
- Figure 425. Processing a SETUP Packet
  1243
- Figure 426. Bulk out Transaction
  1249
- Worst Case Response Time
  1256
- Figure 427. TRDT Max Timing Case
  1258
- OTG Programming Model
  1258
- Figure 428. A-Device SRP
  1259
- Figure 429. B-Device SRP
  1260
- Figure 430. A-Device HNP
  1261
- Figure 431. B-Device HNP
  1263
- HDMI-CEC Controller (HDMI-CEC)
  1265
- HDMI-CEC Controller Main Features
  1265
- Introduction
  1265
- Figure 432. HDMI-CEC Block Diagram
  1266
- HDMI-CEC Block Diagram
  1266
- HDMI-CEC Functional Description
  1266
- HDMI-CEC Pin
  1266
- Table 232. HDMI Pin
  1266
- Bit Timing
  1267
- Figure 433. Message Structure
  1267
- Figure 434. Blocks
  1267
- Message Description
  1267
- Arbitration
  1268
- Figure 435. Bit Timings
  1268
- Figure 436. Signal Free Time
  1268
- Figure 437. Arbitration Phase
  1269
- Figure 438. SFT of Three Nominal Bit Periods
  1269
- SFT Option Bit
  1269
- Bit Error
  1270
- Error Handling
  1270
- Figure 439. Error Bit Timing
  1270
- Message Error
  1270
- Bit Rising Error (BRE)
  1271
- Long Bit Period Error (LBPE)
  1271
- Short Bit Period Error (SBPE)
  1271
- Figure 440. Error Handling
  1272
- Table 233. Error Handling Timing Parameters
  1272
- Figure 441. TXERR Detection
  1273
- Table 234. TXERR Timing Parameters
  1273
- Transmission Error Detection (TXERR)
  1273
- HDMI-CEC Interrupts
  1274
- Table 235. HDMI-CEC Interrupts
  1274
- CEC Control Register (CEC_CR)
  1275
- HDMI-CEC Registers
  1275
- CEC Configuration Register (CEC_CFGR)
  1276
- CEC Interrupt and Status Register (CEC_ISR)
  1279
- CEC Rx Data Register (CEC_RXDR)
  1279
- CEC Tx Data Register (CEC_TXDR)
  1279
- CEC Interrupt Enable Register (CEC_IER)
  1281
- HDMI-CEC Register Map
  1283
- Table 236. HDMI-CEC Register Map and Reset Values
  1283
- Debug Support (DBG)
  1284
- Figure 442. Block Diagram of STM32 MCU and Cortex
  1284
- Overview
  1284
- Reference Arm® Documentation
  1285
- SWJ Debug Port (Serial Wire and JTAG)
  1285
- Figure 443. SWJ Debug Port
  1286
- Mechanism to Select the JTAG-DP or the SW-DP
  1286
- Pinout and Debug Port Pins
  1286
- Flexible SWJ-DP Pin Assignment
  1287
- SWJ Debug Port Pins
  1287
- Table 237. SWJ Debug Port Pins
  1287
- Table 238. Flexible SWJ-DP Pin Assignment
  1287
- Internal Pull-Up and Pull-Down on JTAG Pins
  1288
- Using Serial Wire and Releasing the Unused Debug Pins as Gpios
  1288
- Figure 444. JTAG TAP Connections
  1289
- Stm32F446Xx JTAG TAP Connection
  1289
- Boundary Scan TAP
  1290
- ID Codes and Locking Mechanism
  1290
- MCU Device ID Code
  1290
- Cortex ® -M4 with FPU JEDEC-106 ID Code
  1291
- JTAG Debug Port
  1291
- Table 239. JTAG Debug Port Data Registers
  1291
- SW Debug Port
  1293
- SW Protocol Introduction
  1293
- SW Protocol Sequence
  1293
- Table 240. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
  1293
- SW-DP State Machine (Reset, Idle States, ID Code)
  1294
- Table 241. Packet Request (8-Bits)
  1294
- Table 242. ACK Response (3 Bits)
  1294
- Table 243. DATA Transfer (33 Bits)
  1294
- DP and AP Read/Write Accesses
  1295
- SW-DP Registers
  1295
- Table 244. SW-DP Registers
  1295
- SW-AP Registers
  1296
- AHB-AP (AHB Access Port) - Valid for both JTAG-DP and SW-DP
  1297
- Table 245. Cortex ® -M4 with FPU AHB-AP Registers
  1297
- Core Debug
  1298
- Table 246. Core Debug Registers
  1298
- Capability of the Debugger Host to Connect under System Reset
  1299
- FPB (Flash Patch Breakpoint)
  1299
- DWT (Data Watchpoint Trigger)
  1300
- General Description
  1300
- ITM (Instrumentation Trace Macrocell)
  1300
- Time Stamp Packets, Synchronization and Overflow Packets
  1300
- Table 247. Main ITM Registers
  1301
- ETM (Embedded Trace Macrocell)
  1302
- General Description
  1302
- Signal Protocol, Packet Types
  1302
- Configuration Example
  1303
- Main ETM Registers
  1303
- MCU Debug Component (DBGMCU)
  1303
- Table 248. Main ETM Registers
  1303
- Debug MCU Configuration Register
  1304
- Debug Support for Low-Power Modes
  1304
- Debug Support for Timers, Watchdog, Bxcan and I C
  1304
- Debug MCU APB1 Freeze Register (DBGMCU_APB1_FZ)
  1307
- Debug MCU APB2 Freeze Register (DBGMCU_APB2_FZ)
  1309
- Figure 445. TPIU Block Diagram
  1310
- Introduction
  1310
- TPIU (Trace Port Interface Unit)
  1310
- Table 249. Asynchronous TRACE Pin Assignment
  1311
- Table 250. Synchronous TRACE Pin Assignment
  1311
- TRACE Pin Assignment
  1311
- Table 251. Flexible TRACE Pin Assignment
  1312
- TPUI Formatter
  1313
- TPUI Frame Synchronization Packets
  1313
- Transmission of the Synchronization Frame Packet
  1313
- Asynchronous Mode
  1314
- Synchronous Mode
  1314
- TPIU Registers
  1314
- TRACECLKIN Connection in Stm32F446Xx
  1314
- 33.17.10 Example of Configuration
  1315
- Table 252. Important TPIU Registers
  1315
- DBG Register Map
  1316
- Table 253. DBG Register Map and Reset Values
  1316
- Device Electronic Signature
  1317
- Unique Device ID Register (96 Bits)
  1317
- Flash Memory Size Register
  1318
- Package Data Register
  1318
- Revision History
  1319
- Table 254. Document Revision History
  1319

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