I-Bus; D-Bus; S-Bus; Dma Memory Bus - ST STM32F446 Series Reference Manual

Memory and bus architecture
2.1.1

I-bus

This bus connects the Instruction bus of the Cortex
This bus is used by the core to fetch instructions. The target of this bus is a memory
containing code (internal Flash memory/SRAM or external memories through the FMC).
2.1.2

D-bus

This bus connects the databus of the Cortex
used by the core for literal load and debug access. The target of this bus is a memory
containing code or data (internal Flash memory or external memories through the FMC).
2.1.3

S-bus

This bus connects the system bus of the Cortex
bus is used to access data located in a peripheral or in SRAM. Instructions may also be
fetch on this bus (less efficient than ICode). The targets of this bus are the internal SRAM,
SRAM2, the AHB1 peripherals including the APB peripherals, the AHB2 peripherals and the
external memories through the FMC and QUADSPI.
2.1.4

DMA memory bus

This bus connects the DMA memory bus master interface to the BusMatrix. It is used by the
DMA to perform transfer to/from memories. The targets of this bus are data memories:
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Figure 1. System architecture for STM32F446xx devices

RM0390 Rev 4
®
-M4 with FPU core to the BusMatrix.
®
-M4 with FPU to the BusMatrix. This bus is
®
-M4 with FPU core to a BusMatrix. This
RM0390