Spdifrx Handling; Figure 347. Synchronization Process Scheduling - ST STM32F446 Series Reference Manual

SPDIF receiver interface (SPDIFRX)
27.3.5

SPDIFRX handling

The software can control the state of the SPDIFRX through SPDIFRXEN field. The
SPDIFRX can be into one of the following states:
• STATE_IDLE:
The peripheral is disabled, the SPDIFRX_CLK domain is reset. The PCLK1 domain is
functional.
•
STATE_SYNC:
The peripheral is synchronized to the stream, thresholds are updated regularly, user
and channel status can be read via interrupt of DMA. The audio samples are not
provided to receive buffer.
•
STATE_RCV:
The peripheral is synchronized to the stream, thresholds are updated regularly, user,
channel status and audio samples can be read via interrupt or DMA channels. When
SPDIFRXEN goes to 0b11, the SPDIFRX waits for "B" preamble before starting saving
audio samples.
•
STOP_STATE:
The peripheral is no longer synchronized, the reception of the user, channel status and
audio samples are stopped. It is expected that the software re-starts the SPDIFRX.
The Figure 348
state to the other. The bits under software control are followed by the mention "(SW)", the
bits under IP control are followed by the mention "(HW)".
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Figure 347. Synchronization process scheduling

shows the possible states of the SPDIFRX, and how to transition from one
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