Figure 290. Usart Example Of Synchronous Transmission; Figure 291. Usart Data Clock Timing Diagram (M=0) - ST STM32F446 Series Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
has been written). This means that it is not possible to receive a synchronous data without
transmitting data.
The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. These
bits should not be changed while the transmitter or the receiver is enabled.
It is advised that TE and RE are set in the same instruction in order to minimize the setup
and the hold time of the receiver.
The USART supports master mode only: it cannot receive or send data related to an input
clock (SCLK is always an output).
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Figure 290. USART example of synchronous transmission

Figure 291. USART data clock timing diagram (M=0)

RM0390 Rev 4
RM0390