Rtc Backup Registers (Rtc_Bkpxr) - ST STM32F446 Series Reference Manual

RM0390
Bits 31:28 Reserved, must be kept at reset value
Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit
Bits 23:15 Reserved, must be kept at reset value
Bits 14:0 SS[14:0]: Sub seconds value
Note: This register can be written only when ALRBIE is reset in RTC_CR register, or in
initialization mode.
This register is write protected.The write access procedure is described in
write protection
22.6.20

RTC backup registers (RTC_BKPxR)

Address offset: 0x50 to 0x9C
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 BKP[31:0]
0x0: No comparison on sub seconds for Alarm B. The alarm is set when the seconds unit is
incremented (assuming that the rest of the fields match).
0x1: SS[14:1] are don't care in Alarm B comparison. Only SS[0] is compared.
0x2: SS[14:2] are don't care in Alarm B comparison. Only SS[1:0] are compared.
0x3: SS[14:3] are don't care in Alarm B comparison. Only SS[2:0] are compared.
...
0xC: SS[14:12] are don't care in Alarm B comparison. SS[11:0] are compared.
0xD: SS[14:13] are don't care in Alarm B comparison. SS[12:0] are compared.
0xE: SS[14] is don't care in Alarm B comparison. SS[13:0] are compared.
0xF: All 15 SS bits are compared and must match to activate alarm.
The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be
different from 0 only after a shift operation.
This value is compared with the contents of the synchronous prescaler's counter to
determine if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
The application can write or read data to and from these registers.
They are powered-on by V
System reset, and their contents remain valid when the device operates in low-power mode.
This register is reset on a tamper detection event, as long as TAMPxF=1.
24 23 22
BKP[31:16]
rw rw rw
8 7 6
BKP[15:0]
rw rw rw
when V is switched off, so that they are not reset by
BAT DD
RM0390 Rev 4
Real-time clock (RTC)
RTC register
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw w
17 16
rw rw
1 0
rw rw
689/1328
691