Table 19. Standby Mode Entry And Exit - ST STM32F446 Series Reference Manual

RM0390
Refer to
In Standby mode, the following features can be selected by programming individual control
bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 20.3: IWDG functional
• Real-time clock (RTC): this is configured by the RTCEN bit in the backup domain
control register (RCC_BDCR)
•
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
•
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
backup domain control register (RCC_BDCR)
Exiting Standby mode
The microcontroller exits Standby mode according to
status flag in the
was in Standby mode. All registers are reset after wakeup from standby except for
power control/status register
Refer to
Standby mode
Mode entry
Mode exit
Wakeup latency
Table 19 for more details on how to enter Standby mode.
PWR power control/status register (PWR_CSR)
(PWR_CSR).
Table 19 for more details on how to exit Standby mode.

Table 19. Standby mode entry and exit

WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP is set in Cortex
register
– PDDS bit is set in Power Control register (PWR_CR)
– no interrupt (for WFI or event (for WFE) is pending
– WUF bit is cleared in Power Control/Status register (PWR_CR)
– the RTC flag corresponding to the chosen wakeup source (RTC Alarm A,
RTC Alarm B, RTC wakeup, Tamper or Timestamp flags) is cleared
On Return from ISR while:
– SLEEPDEEP bit is set in Cortex
register and
– SLEEPONEXIT = 1 and
– PDDS bit is set in Power Control register (PWR_CR) and
– no interrupt is pending and
– WUF bit is cleared in Power Control/Status register (PWR_SR) and
– the RTC flag corresponding to the chosen wakeup source (RTC Alarm A,
RTC Alarm B, RTC wakeup, Tamper or Timestamp flags) is cleared
WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
tamper event, time stamp event, external reset in NRST pin, IWDG reset.
Reset phase.
description.
Exiting low power
Description
®
-M4 with FPU with FPU System Control
®
-M4 with FPU with FPU System Control
RM0390 Rev 4
Power controller (PWR)
mode. The SBF
indicates that the MCU
PWR
107/1328
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