I 2 S Master Mode - ST STM32F446 Series Reference Manual

Serial peripheral interface/ inter-IC sound (SPI/I2S)
Table 164. Audio-frequency precision using standard 8 MHz HSE
SYSCLK
(MHz)
48
48
48
48
48
48
48
1. This table gives only example values for different clock configurations. Other configurations allowing
optimum clock precision are possible.
2
26.6.5 I S master mode
2
The I S can be configured in master mode. This means that the serial clock is generated on
the CK pin as well as the Word Select signal WS. Master clock (MCK) may be output or not,
controlled by the MCKOE bit in the SPIx_I2SPR register.
Procedure
1. Select the I2SDIV[7:0] bits in the SPIx_I2SPR register to define the serial clock baud
rate to reach the proper audio sample frequency. The ODD bit in the SPIx_I2SPR
register also has to be defined.
2. Select the CKPOL bit to define the steady level for the communication clock. Set the
MCKOE bit in the SPIx_I2SPR register if the master clock MCK needs to be provided
to the external ADC audio component (the I2SDIV and ODD values should be
computed depending on the state of the MCK output, for more details refer to
Section 26.6.4: Clock
3. Set the I2SMOD bit in the SPIx_I2SCFGR register to activate the I
choose the I
through the DATLEN[1:0] bits and the number of bits per channel by configuring the
CHLEN bit. Select also the I
through the I2SCFG[1:0] bits in the SPIx_I2SCFGR register.
4. If needed, select all the potential interrupt sources and the DMA capabilities by writing
the SPIx_CR2 register.
5. The I2SE bit in SPIx_I2SCFGR register must be set.
WS and CK are configured in output mode. MCK is also an output, if the MCKOE bit in
SPIx_I2SPR is set.
Transmission sequence
The transmission sequence begins when a half-word is written into the Tx buffer.
Lets assume the first data written into the Tx buffer corresponds to the left channel data.
When data are transferred from the Tx buffer to the shift register, TXE is set and data
corresponding to the right channel have to be written into the Tx buffer. The CHSIDE flag
880/1328
Data
I2SDIV I2SODD
length
32 4 1
16 6 0
32 6 0
16 8 1
32 8 1
16 11 1
32 11 1
generator).
2
S standard through the I2SSTD[1:0] and PCMSYNC bits, the data length
2
S master mode and direction (Transmitter or Receiver)
RM0390 Rev 4
Target f
S
MCLK
(Hz)
Yes 22050
Yes 16000
Yes 16000
Yes 11025
Yes 11025
Yes 8000
Yes 8000
RM0390
(1)
(continued)
Real f (KHz) Error
S
20833.333 5.5178%
15625 2.3438%
15625 2.3438%
11029.4118 0.0400%
11029.4118 0.0400%
8152.17391 1.9022%
8152.17391 1.9022%
2
S functions and