Lse Clock; Lsi Clock; System Clock (Sysclk) Selection - ST STM32F446 Series Reference Manual

Reset and clock control (RCC)
The PLLI2S and PLLSAI use the same input clock as PLL (PLLSRC bit is common to both
PLLs). However, the PLLI2S and PLLSAI have dedicated enable/disable and division
factors (M, N, P, R and R) configuration bits. Once the PLLI2S and PLLSAI are enabled, the
configuration parameters cannot be changed.
The three PLLs are disabled by hardware when entering Stop and Standby modes, or when
an HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock.
PLL configuration register (RCC_PLLCFGR),RCC clock configuration register
(RCC_CFGR), and
used to configure PLL, PLLI2S, and PLLSAI.
6.2.4

LSE clock

The LSE clock is generated from a 32.768 kHz low-speed external crystal or ceramic
resonator. It has the advantage providing a low-power but highly accurate clock source to
the real-time clock peripheral (RTC) for clock/calendar or other timing functions.
The LSE oscillator is switched on and off using the LSEON bit in
control register
The LSERDY flag in the
LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released
until this bit is set by hardware. An interrupt can be generated if enabled in the
interrupt register
External source (LSE bypass)
In this mode, an external clock source must be provided. It must have a frequency up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the
domain control register
with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be
left HI-Z. See
6.2.5

LSI clock

The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The
clock frequency is around 32 kHz. For more details, refer to the electrical characteristics
section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the
status register
The LSIRDY flag in the
speed internal oscillator is stable or not. At startup, the clock is not released until this bit is
set by hardware. An interrupt can be generated if enabled in the
(RCC_CIR).
6.2.6

System clock (SYSCLK) selection

After a system reset, the HSI oscillator is selected as the system clock. When a clock source
is used directly or through PLL as the system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source that is not yet ready is
selected, the switch occurs when the clock source is ready. Status bits in the
122/1328
RCC Dedicated Clock Configuration Register (RCC_DCKCFGR)
(RCC_BDCR).
RCC Backup domain control register (RCC_BDCR)
(RCC_CIR).
(RCC_BDCR). The external clock signal (square, sinus or triangle)
Figure 15.
(RCC_CSR).
RCC clock control & status register (RCC_CSR)
RM0390 Rev 4
RM0390
can be
RCC Backup domain
indicates if the
RCC clock
RCC Backup
RCC clock control &
indicates if the low-
RCC clock interrupt register
RCC clock
RCC