Clocking Strategy; Dma Interface; Table 168. Minimum Spdifrx_Clk Frequency Versus Audio Sampling Rate; Figure 352. S/Pdif Overrun Error When Rxsteo = 1 - ST STM32F446 Series Reference Manual

RM0390
27.3.9

Clocking strategy

The SPDIFRX block needs two different clocks:
•
The APB1 clock (PCLK1), which is used for the register interface,
•
The SPDIFRX_CLK which is mainly used by the SPDIFRX_DC part. Those clocks are
not supposed to be phase locked, so all signals crossing those clock domains are re-
synchronized (SYNC block on
In order to decode properly the incoming S/PDIF stream the SPDIFRX_DC shall re-sample
the received data with a clock at least 11 times higher than the maximum symbol rate, or
704 times higher than the audio sample rate. For example if the user expects to receive a
symbol rate to up to 12.288 MHz, the sample rate shall be at least 135.2 MHz. The clock
used by the SPDIFRX_DC is the SPDIFRX_CLK.
The frequency of the PCLK1 must be at least equal to the symbol rate.

Table 168. Minimum SPDIFRX_CLK frequency versus audio sampling rate

Symbol Rate
3.072 MHz
6.144 MHz
12.288 MHz
27.3.10

DMA Interface

The SPDIFRX interface is able to perform communication using the DMA.
Note: The user should refer to product specifications for availability of the DMA controller.
The SPDIFRX offers two independent DMA channels:
•
A DMA channel dedicated to the data transfer
•
A DMA channel dedicated to the channel status and user data transfer
The DMA mode for the data can be enabled for reception by setting the RXDMAEN bit in the
SPDIFRX_CR register. In this case, as soon as the SPDIFRX_DR is not empty, the

Figure 352. S/PDIF overrun error when RXSTEO = 1

Figure
Minimum SPDIFRX_CLK frequency
33.8 MHz
67.6 MHz
135.2 MHz
RM0390 Rev 4
SPDIF receiver interface (SPDIFRX)
338).
For 48 kHz stream
For 96 kHz stream
For 192 kHz stream
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