Data Input Register (Spdifrx_Fmt2_Dr) - ST STM32F446 Series Reference Manual

SPDIF receiver interface (SPDIFRX)
27.5.7

Data input register (SPDIFRX_FMT2_DR)

Address offset: 0x10
Reset value: 0x0000 0000
This register can take 3 different formats according to DRFMT.
The data format proposed when DRFMT = 0b10, is dedicated to non-linear mode, as only
16 bits are used (bits 23 to 8 from S/PDIF sub-frame).
31 30 29
r r r
15 14 13
r r r
Bits 31:16 DRNL2[15:0]: Data value
This field contains the Channel A
Bits 15:0 DRNL1[15:0]: Data value
This field contains the Channel B
926/1328
28 27 26 25
r r r r
12 11 10 9
r r r r
24 23 22
DRNL2[15:0]
r r r
8 7 6
DRNL1[15:0]
r r r
RM0390 Rev 4
21 20 19 18
r r r r
5 4 3 2
r r r r
RM0390
17 16
r r
1 0
r r