Flexible memory controller (FMC)
Bit number
12
11
10
9
8
7
6
5-4
3-2
1
0
Bit number
31-30
29:28
27-24
23-20
19-16
15-8
7-4
3-0
286/1328
Table 72. FMC_BCRx bit fields (continued)
Bit name
WREN
0x1
WAITCFG
0x0
Reserved
0x0
WAITPOL
to be set according to memory
BURSTEN
no effect on synchronous write
Reserved
0x1
FACCEN
Set according to memory support
MWID
As needed
MTYP
0x1
MUXEN
As needed
MBKEN
0x1
Table 73. FMC_BTRx bit fields
Bit name
Reserved
0x0
ACCMOD
0x0
DATLAT
Data latency
0x0 to get CLK = HCLK (not supported)
CLKDIV
0x1 to get CLK = 2 × HCLK
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK).
DATAST
Don't care
ADDHLD
Don't care
ADDSET
Don't care
RM0390 Rev 4
Value to set
Value to set
RM0390
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