Fmpi2C Registers; Control Register 1 (Fmpi2C_Cr1) - ST STM32F446 Series Reference Manual

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
23.7

FMPI2C registers

Refer to
The peripheral registers are accessed by words (32-bit).
23.7.1

Control register 1 (FMPI2C_CR1)

Address offset: 0x00
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x
FMPI2CCLK.
31 30 29
Res. Res. Res.
15 14 13
RXDMA TXDMA
Res.
EN EN
rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 PECEN: PEC enable
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Bit 22 ALERTEN: SMBus alert enable
Device mode (SMBHEN=0):
Host mode (SMBHEN=1):
Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO.
Bit 21 SMBDEN: SMBus Device Default address enable
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
742/1328
Section 1.1 on page 51
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
ANF
DNF
OFF
rw rw
0: PEC calculation disabled
1: PEC calculation enabled
Refer to Section 23.3: FMPI2C
0: Releases SMBA pin high and Alert Response Address Header disabled: 0001100x
followed by NACK.
1: Drives SMBA pin low and Alert Response Address Header enables: 0001100x followed
by ACK.
0: SMBus Alert pin (SMBA) not supported.
1: SMBus Alert pin (SMBA) supported.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Refer to Section 23.3: FMPI2C
0: Device default address disabled. Address 0b1100001x is NACKed.
1: Device default address enabled. Address 0b1100001x is ACKed.
Refer to Section 23.3: FMPI2C
for a list of abbreviations used in register descriptions.
24 23 22
ALERT SMBD
Res. PECEN
EN
rw rw
8 7 6
STOP
ERRIE TCIE
rw rw
implementation.
implementation.
implementation.
RM0390 Rev 4
21 20 19 18
SMBH
GCEN Res.
EN EN
rw rw rw
5 4 3 2
NACK ADDR
RXIE
IE IE IE
rw rw rw rw
RM0390
17 16
NOSTR
SBC
ETCH
rw rw
1 0
TXIE PE
rw rw