Disabling The Sai; Sai Dma Interface - ST STM32F446 Series Reference Manual

RM0390
Codec not ready (CNRDY AC'97)
The CNRDY flag in the SAI_xSR register is relevant only if the SAI audio block is configured
to operate in AC'97 mode (PRTCFG[1:0] = 10 in the SAI_xCR1 register). If CNRDYIE bit is
set in the SAI_xIM register, an interrupt is generated when the CNRDY flag is set.
CNRDY is asserted when the Codec is not ready to communicate during the reception of
the TAG 0 (slot0) of the AC'97 audio frame. In this case, no data will be automatically stored
into the FIFO since the Codec is not ready, until the TAG 0 indicates that the Codec is ready.
All the active slots defined in the SAI_xSLOTR register will be captured when the Codec is
ready.
To clear CNRDY flag, CCNRDY bit must be set in the SAI_xCLRFR register.
Wrong clock configuration in master mode (with NODIV = 0)
When the audio block operates as a master (MODE[1] = 0) and NODIV bit is equal to 0, the
WCKCFG flag is set as soon as the SAI is enabled if the following conditions are met:
•
(FRL+1) is not a power of 2, and
•
(FRL+1) is not between 8 and 256.
MODE, NODIV, and SAIEN bits belong to SAI_xCR1 register and FRL to SAI_xFRCR
register.
If WCKCFGIE bit is set, an interrupt is generated when WCKCFG flag is set in the SAI_xSR
register. To clear this flag, set CWCKCFG bit in the SAI_xCLRFR register.
When WCKCFG bit is set, the audio block is automatically disabled, thus performing a
hardware clear of SAIEN bit.
28.3.14

Disabling the SAI

The SAI audio block can be disabled at any moment by clearing SAIEN bit in the SAI_xCR1
register. All the already started frames are automatically completed before the SAI is stops
working. SAIEN bit remains High until the SAI is completely switched-off at the end of the
current audio frame transfer.
If an audio block in the SAI operates synchronously with the other one, the one which is the
master must be disabled first.
28.3.15

SAI DMA interface

To free the CPU and to optimize bus bandwidth, each SAI audio block has an independent
DMA interface to read/write from/to the SAI_xDR register (to access the internal FIFO).
There is one DMA channel per audio sub-block supporting basic DMA request/acknowledge
protocol.
To configure the audio sub-block for DMA transfer, set DMAEN bit in the SAI_xCR1 register.
The DMA request is managed directly by the FIFO controller depending on the FIFO
threshold level (for more details refer to
direction is linked to the SAI audio sub-block configuration:
• If the audio block operates as a transmitter, the audio block FIFO controller outputs a
DMA request to load the FIFO with data written in the SAI_xDR register.
•
If the audio block is operates as a receiver, the DMA request is related to read
operations from the SAI_xDR register.
Section 28.3.9: Internal
RM0390 Rev 4
Serial audio interface (SAI)
FIFOs). DMA transfer
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