ST STM32F446 Series Reference Manual page 147

RM0390
31 30 29 28
DAC PWR
Res. Res.
EN EN
rw rw
15 14 13 12
SPI3 SPI2
Res. Res.
EN EN
rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACEN: DAC interface clock enable
This bit is set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Bit 28 PWREN: Power interface clock enable
This bit is set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Bit 27 CECEN: CEC interface clock enable
This bit is set and cleared by software.
0: CEC interface clock disabled
1: CEC interface clock enabled
Bit 26 CAN2EN: CAN 2 clock enable
This bit is set and cleared by software.
0: CAN 2 clock disabled
1: CAN 2 clock enabled
Bit 25 CAN1EN: CAN 1 clock enable
This bit is set and cleared by software.
0: CAN 1 clock disabled
1: CAN 1 clock enabled
Bit 24 FMPI2C1EN: FMPI2C1 clock enable
This bit is set and cleared by software.
0: FMPI2C1 clock disabled
1: FMPI2C1 clock enabled
Bit 23 I2C3EN: I2C3 clock enable
This bit is set and cleared by software.
0: I2C3 clock disabled
1: I2C3 clock enabled
Bit 22 I2C2EN: I2C2 clock enable
This bit is set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
Bit 21 I2C1EN: I2C1 clock enable
This bit is set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
27 26 25 24
CEC CAN2 CAN1 FMPI2C1
EN EN EN EN
rw rw rw rw
11 10 9 8
WWDG TIM14
Res. Res.
EN EN
rw rw
RM0390 Rev 4
23 22 21 20
I2C3 I2C2 I2C1 UART5
EN EN EN EN
rw rw rw rw
7 6 5 4
TIM13 TIM12 TIM7 TIM6
EN EN EN EN
rw rw rw rw
Reset and clock control (RCC)
19 18 17
UART4 USART3 USART2
EN EN EN
rw rw rw
3 2 1
TIM5 TIM4 TIM3
EN EN EN
rw rw rw
16
SPDIFRX
EN
rw
0
TIM2
EN
rw
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