ST STM32F446 Series Reference Manual page 160

Reset and clock control (RCC)
Reset value: 0x0000 0000, reset by Backup domain reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
The LSEON, LSEBYP, RTCSEL and RTCEN bits in the
register (RCC_BDCR)
write-protected and the DBP bit in the
before these can be modified. Refer to
information. These bits are only reset after a Backup domain Reset (see
Backup domain
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
RTCEN Res. Res. Res.
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 BDRST: Backup domain software reset
This bit is set and cleared by software.
0: Reset not activated
1: Resets the entire Backup domain
Note: The BKPSRAM is not affected by this reset, the only way of resetting the BKPSRAM is
Bit 15 RTCEN: RTC clock enable
This bit is set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
These bits are set by software to select the clock source for the RTC. Once the RTC clock
source has been selected, it cannot be changed anymore unless the Backup domain is
reset. The BDRST bit can be used to reset them.
00: No clock
01: LSE oscillator clock used as the RTC clock
10: LSI oscillator clock used as the RTC clock
11: HSE oscillator clock divided by a programmable prescaler (selection through the
RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC
clock
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 LSEMOD: External low-speed oscillator mode
This bit is set and cleared by software to select the low speed oscillator crystal mode. Two
power modes are available. This bit can be written only when the LSE clock is disabled.
0: LSE oscillator "low power" mode selection
1: LSE oscillator "high drive" mode selection
160/1328
are in the Backup domain. As a result, after Reset, these bits are
reset). Any internal or external Reset will not have any effect on these bits.
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. RTCSEL[1:0]
rw rw
through the Flash interface when a protection level change from level 1 to level 0 is
requested.
RM0390 Rev 4
RCC Backup domain control
PWR power control register (PWR_CR)
Section 6.1.1: System reset on page 116
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
Res. Res. Res. Res.
RM0390
has to be set
for further
Section 6.1.3:
19 18 17
Res. Res. Res.
3 2 1
LSEMOD LSEBYP LSERDY LSEON
rw rw r
16
BDRST
rw
0
rw