Dcmi Interrupt Enable Register (Dcmi_Ier) - ST STM32F446 Series Reference Manual

Advanced arm-based 32-bit mcus

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DCMI interrupt enable register (DCMI_IER)

Address offset: 0x0C

Reset value: 0x0000 0000

The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set,

the corresponding interrupt is enabled. This register is accessible in both read and write.

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 LINE_IE: Line interrupt enable

0: No interrupt generation when the line is received

1: An Interrupt is generated when a line has been completely received

Bit 3 VSYNC_IE: DCMI_VSYNC interrupt enable

0: No interrupt generation

1: An interrupt is generated on each DCMI_VSYNC transition from the inactive to

the active state

The active state of the DCMI_VSYNC signal is defined by the VSPOL bit.

Bit 2 ERR_IE: Synchronization error interrupt enable

0: No interrupt generation

1: An interrupt is generated if the embedded synchronization codes are not

received in the correct order.

Note: This bit is available only in embedded synchronization mode.

Bit 1 OVR_IE: Overrun interrupt enable

0: No interrupt generation

1: An interrupt is generated if the DMA was not able to transfer the last data

before new data (32-bit) are received.

Bit 0 FRAME_IE: Capture complete interrupt enable

0: No interrupt generation

1: An interrupt is generated at the end of each received frame/crop window (in

RM0390 Rev 4

Digital camera interface (DCMI)

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