Spi Interrupts; Table 163. Spi Interrupt Requests - ST STM32F446 Series Reference Manual

Serial peripheral interface/ inter-IC sound (SPI/I2S)
has to be reset between sessions by the SPI disable sequence by re-enabling the CRCEN
bit described above at both master and slave sides, else the CRC calculation can be
corrupted at this specific mode.
26.5

SPI interrupts

During SPI communication an interrupts can be generated by the following events:
•
Transmit Tx buffer ready to be loaded
•
Data received in Rx buffer
•
Master mode fault
•
Overrun error
•
TI frame format error
Interrupts can be enabled and disabled separately.
Transmit Tx buffer ready to be loaded
Data received in Rx buffer
Master Mode fault event
Overrun error
CRC error
TI frame format error
868/1328

Table 163. SPI interrupt requests

Interrupt event
RM0390 Rev 4
Event flag Enable Control bit
TXE
RXNE
MODF
OVR
CRCERR
FRE
RM0390
TXEIE
RXNEIE
ERRIE