Spdif Receiver Interface (Spdifrx); Spdifrx Interface Introduction; Spdifrx Main Features; Spdifrx Functional Description - ST STM32F446 Series Reference Manual

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SPDIF receiver interface (SPDIFRX)

27.1

SPDIFRX interface introduction

The SPDIFRX interface handles S/PDIF audio protocol.
27.2

SPDIFRX main features

•
Up to 4 inputs available
•
Automatic symbol rate detection
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Maximum symbol rate: 12.288 MHz
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Stereo stream from 32 to 192 kHz supported
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Supports Audio IEC-60958 and IEC-61937, consumer applications
•
SOPDs B, M and W insertion inside S/PDIF flow
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Parity bit management
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Communication using DMA for audio samples
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Communication using DMA for control and user channel information
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Interrupt capabilities
27.3

SPDIFRX functional description

The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS.
The receiver provides all the necessary features to detect the symbol rate, and decode the
incoming data. It is possible to use a dedicated path for the user and channel information in
order to ease the interface handling.
The SPDIFRX_DC block is responsible of the decoding of the S/PDIF stream received from
SPDIFRX_IN[4:1] inputs. This block re-sample the incoming signal, decode the manchester
stream, recognize frames, sub-frames and blocks elements. It delivers to the REG_IF part,
decoded data, and associated status flags.
This peripheral can be fully controlled via the APB1 bus, and can handle two DMA channels:
•
A DMA channel dedicated to the transfer of audio samples
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A DMA channel dedicated to the transfer of IEC60958 channel status and user
information
Interrupt services are also available either as an alternative function to the DMA, or for
signaling error or key status of the peripheral.
The SPDIFRX also offers a signal named spdifrx_frame_sync, which toggles every time
that a sub-frame's preamble is detected. So the duty cycle will be 50%, and the frequency
equal to the frame rate.
This signal can be connected to timer events, in order to compute frequency drift.
SPDIF receiver interface (SPDIFRX)
Figure 338 shows a simplified block diagram.
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