Channel Status Register (Spdifrx_Csr); Debug Information Register (Spdifrx_Dir) - ST STM32F446 Series Reference Manual

Advanced arm-based 32-bit mcus

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Channel status register (SPDIFRX_CSR)

Address offset: 0x14

Reset value: 0x0000 0000

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 SOB: Start Of Block

This bit indicates if the bit CS[0] corresponds to the first bit of a new block

0: CS[0] is not the first bit of a new block

1: CS[0] is the first bit of a new block

Bits 23:16 CS[7:0]: Channel A status information

Bit CS[0] is the oldest value

Bits 15:0 USR[15:0]: User data information

Bit USR[0] is the oldest value, and comes from channel A, USR[1] comes channel B.

So USR[n] bits come from channel A is n is even, otherwise they come from channel B.

Address offset: 0x18

Reset value: 0x0000 0000

Bits 31:29 Reserved, must be kept at reset value.

SPDIF receiver interface (SPDIFRX)

RM0390 Rev 4

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