Debug Mode; Tim6&Tim7 Registers; Tim6&Tim7 Control Register 1 (Timx_Cr1); Figure 236. Control Circuit In Normal Mode, Internal Clock Divided By 1 - ST STM32F446 Series Reference Manual

Basic timers (TIM6&TIM7)

Figure 236. Control circuit in normal mode, internal clock divided by 1

19.3.4

Debug mode

When the microcontroller enters the debug mode (Cortex
TIMx counter either continues to work normally or stops, depending on the
DBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to
Section 33.16.2: Debug support for timers, watchdog, bxCAN and
19.4 TIM6&TIM7 registers
Refer to
The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read
accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
19.4.1 TIM6&TIM7 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 ARPE: Auto-reload preload enable
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One-pulse mode
634/1328
Section 1.1 on page 51
12 11 10 9
Res. Res. Res.
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit).
for a list of abbreviations used in register descriptions.
8 7 6 5
Res. ARPE Res. Res.
rw
RM0390 Rev 4
®
-M4 with FPU core - halted), the
I2C.
4 3 2
Res. OPM URS
rw rw
RM0390
1 0
UDIS CEN
rw rw