Sai Functional Description; Sai Block Diagram; Figure 354. Sai Functional Block Diagram - ST STM32F446 Series Reference Manual

Serial audio interface (SAI)
28.3

SAI functional description

28.3.1

SAI block diagram

Figure 354
external signals.
The SAI is mainly composed of two audio sub-blocks with their own clock generator. Each
audio block integrates a 32-bit shift register controlled by their own functional state machine.
Data are stored or read from the dedicated FIFO. FIFO may be accessed by the CPU, or by
DMA in order to leave the CPU free during the communication. Each audio block is
independent. They can be synchronous with each other.
An I/O line controller manages a set of 4 dedicated pins (SD, SCK, FS, MCLK) for a given
audio block in the SAI. Some of these pins can be shared if the two sub-blocks are declared
as synchronous to leave some free to be used as general purpose I/Os. The MCLK pin can
be output, or not, depending on the application, the decoder requirement and whether the
audio block is configured as the master.
If one SAI is configured to operate synchronously with another one, even more I/Os can be
freed (except for pins SD_x).
The functional state machine can be configured to address a wide range of audio protocols.
Some registers are present to set-up the desired protocols (audio frame waveform
generator).
932/1328
shows the SAI block diagram while

Figure 354. SAI functional block diagram

RM0390 Rev 4
Table 171 and Table 172
RM0390
list SAI internal and