ST STM32F446 Series Reference Manual page 324

Flexible memory controller (FMC)
Offset Register
FMC_BWTR3
0x114
Reset value
FMC_BWTR4
0x11C
Reset value
FMC_PCR
0x80
Reset value
FMC_SR
0x84
Reset value
FMC_PMEM
0x88
Reset value 1
FMC_PATT
0x8C
Reset value 1
FMC_ECCR
0x94
Reset value 0
FMC_SDCR1
0x140
Reset value
FMC_SDCR2
0x144
Reset value
FMC_SDTR1
0x148
Reset value
FMC_SDTR2
0x14C
Reset value
FMC_SDCMR
0x150
Reset value
FMC_SDRTR
0x154
Reset value
FMC_SDSR
0x158
Reset value
Refer to
324/1328
Table 80. FMC register map (continued)
0 0
0 0
MEMHIZx[7:0]
1 1 1 1 1 0 0 1
ATTHIZ[7:0]
1 1 1 1 1 0 0 1
0 0 0 0 0 0 0 0
TRCD[3:0] TRP[3:0]
1 1 1 1 1
TRCD[3:0] TRP[3:0]
1 1 1 1 1
Section 2.2.2 on page 56
BUSTURN[3:0]
1 1 1 1 1
BUSTURN[3:0]
1 1 1 1 1
ECCPS
TAR[3:0]
[2:0]
0 0 0 0 0
MEMHOLDx[7:0]
1 1 1 1 1 0 0 1
ATTHOLD[7:0]
1 1 1 1 1 0 0 1
ECCx[31:0]
0 0 0 0 0 0 0 0
RPIPE[
TWR[3:0] TRC[3:0]
1 1 1 1 1 1 1 1
TWR[3:0] TRC[3:0]
1 1 1 1 1 1 1 1
MRD[12:0]
0 0 0 0 0 0 0
for the register boundary addresses.
RM0390 Rev 4
DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
1 1 1 1 1 1 1 1
DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
1 1 1 1 1 1 1 1
TCLR[3:0]
0 0 0 0 0 0
MEMWAITx[7:0]
1 1 1 1 1 0 0 1
ATTWAIT[7:0]
1 1 1 1 1 0 0 1
0 0 0 0 0 0 0 0
SDCLK CAS
WP NB
1:0] [1:0] [1:0]
0 0 0 1 1 0 1 0
SDCLK CAS
WP NB
[1:0] [1:0]
0 1 1 0 1 0
TRAS[3:0] TXSR[3:0]
1 1 1 1 1 1 1 1
TRAS[3:0] TXSR[3:0]
1 1 1 1 1 1 1 1
NRFS[3:0]
0 0 0 0 0 0 0 0
COUNT[12:0]
0 0 0 0 0 0 0 0
RM0390
1 1 1 1 1 1 1
1 1 1 1 1 1 1
PWID
[1:0]
0 0 1 1 0 0
1 0 0 0 0 0 0
MEMSETx[7:0]
1 1 1 1 1 0 0
ATTSET[7:0]
1 1 1 1 1 0 0
0 0 0 0 0 0 0
MWID
NR[1:0] NC
[1:0]
0 1 0 0 0 0 0
MWID
NR[1:0] NC
[1:0]
0 1 0 0 0 0 0
TMRD[3:0]
1 1 1 1 1 1 1
TMRD[3:0]
1 1 1 1 1 1 1
MODE[2:0]
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0