ST STM32F446 Series Reference Manual page 922

SPDIF receiver interface (SPDIFRX)
Bit 5 SYNCD: Synchronization Done
This bit is set by hardware when the initial synchronization phase is properly completed.
This flag is cleared by writing a 1 to its corresponding bit on SPDIFRX_CLR_SR register.
An interrupt is generated if SYNCDIE = 1 in the SPDIFRX_IMR register
0: Synchronization is pending
1: Synchronization is completed
Bit 4 SBD: Synchronization Block Detected
This bit is set by hardware when a "B" preamble is detected
This flag is cleared by writing a 1 to its corresponding bit on SPDIFRX_CLR_SR register.
An interrupt is generated if SBLKIE = 1 in the SPDIFRX_IMR register
0: No "B" preamble detected
1: "B" preamble has been detected
Bit 3 OVR: Overrun error
This bit is set by hardware when a received data is ready to be transferred in the SPDIFRX_DR
register while RXNE = 1 and both SPDIFRX_DR and RX_BUF are full.
This flag is cleared by writing a 1 to its corresponding bit on SPDIFRX_CLR_SR register.
An interrupt is generated if OVRIE=1 in the SPDIFRX_IMR register.
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set, the SPDIFRX_DR register content will not be lost but the last data
received will.
Bit 2 PERR: Parity error
This bit is set by hardware when the data and status bits of the sub-frame received contain an odd
number of 0 and 1.
This flag is cleared by writing a 1 to its corresponding bit on SPDIFRX_CLR_SR register.
An interrupt is generated if PIE = 1 in the SPDIFRX_IMR register.
0: No parity error
1: Parity error
Bit 1 CSRNE: The Control Buffer register is not empty
This bit is set by hardware when a valid control information is ready.
This flag is cleared when reading SPDIFRX_CSR register.
An interrupt is generated if CBRDYIE = 1 in the SPDIFRX_IMR register
0: No control word available on SPDIFRX_CSR register
1: A control word is available on SPDIFRX_CSR register
Bit 0 RXNE: Read data register not empty
This bit is set by hardware when a valid data is available into SPDIFRX_DR register.
This flag is cleared by reading the SPDIFRX_DR register.
An interrupt is generated if RXNEIE=1 in the SPDIFRX_IMR register.
0: Data is not received
1: Received data is ready to be read.
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